STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Serial peripheral interface (SPI)
Figure 224. Operations required to receive 0x3478AE
First read from Data register
Second read from Data register
conditioned by RXNE = ‘1’ conditioned by RXNE = ‘1’
0x0034
Only the 8 LSB bits of the half-word
are significant. Whatever the 8 MSBs,
a field of 0x00 is forced instead
0x78AE
Figure 225. LSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0
CK
WS
SD
16-bit data
0 forced
MSB
Transmission
16-bit remaining
Reception
LSB
Channel left 32-bit
Channel right
When 16-bit data frame extended to 32-bit channel frame is selected during the I 2 S
configuration phase, Only one access to SPI_DR is required. The 16 remaining bits are
forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it corresponds
to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit),
the operation shown in Figure 226 is required.
Figure 226. Example
Only one access to SPI_DR
0X76A3
In transmission mode, when TXE is asserted, the application has to write the data to be
transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit).
TXE is asserted again as soon as the effective data (0x76A3) is sent on SD.
In reception mode, RXNE is asserted as soon as the significant half-word is received (and
not the 0x0000 field).
In this way, more time is provided between two write or read operations to prevent underrun
or overrun conditions.
Doc ID 13902 Rev 9 605/995