STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Ethernet (ETH): media access control (MAC) with DMA controller
RM0008
The algorithm is as follows:
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At time MasterSyncTime (n) the master sends the slave clock a Sync message. The
slave receives this message when its local clock is SlaveClockTime (n) and computes
MasterClockTime (n) as:
MasterClockTime (n) = MasterSyncTime (n) + MasterToSlaveDelay (n)
The master clock count for current Sync cycle, MasterClockCount (n) is given by:
MasterClockCount (n) = MasterClockTime (n) – MasterClockTime (n – 1) (assuming
that MasterToSlaveDelay is the same for Sync cycles n and n – 1)
● The slave clock count for current Sync cycle, SlaveClockCount (n) is given by:
SlaveClockCount (n) = SlaveClockTime (n) – SlaveClockTime (n – 1)
● The difference between master and slave clock counts for current Sync cycle,
ClockDiffCount (n) is given by:
ClockDiffCount (n) = MasterClockCount (n) – SlaveClockCount (n)
● The frequency-scaling factor for slave clock, FreqScaleFactor (n) is given by:
FreqScaleFactor (n) = (MasterClockCount (n) + ClockDiffCount (n)) /
SlaveClockCount (n)
● The frequency compensation value for Addend register, FreqCompensationValue (n) is
given by:
FreqCompensationValue (n) = FreqScaleFactor (n) × FreqCompensationValue (n – 1)
In theory, this algorithm achieves lock in one Sync cycle; however, it may take several
cycles, due to changing network propagation delays and operating conditions.
This algorithm is self-correcting: if for any reason the slave clock is initially set to a value
from the master that is incorrect, the algorithm corrects it at the cost of more Sync cycles.
Programming steps for system time generation initialization
Note:
The time stamping feature can be enabled by setting bit 0 in the Time stamp control register
(ETH__PTPTSCR). However, it is essential to initialize the time stamp counter after this bit
is set to start time stamp operation. The proper sequence is the following:
1. Mask the Time stamp trigger interrupt by setting bit 9 in the MACIMR register.
2. Program Time stamp register bit 0 to enable time stamping.
3. Program the Subsecond increment register based on the PTP clock frequency.
4. If you are using the Fine correction method, program the Time stamp addend register
and set Time stamp control register bit 5 (addend register update).
5. Poll the Time stamp control register until bit 5 is cleared.
6. To select the Fine correction method (if required), program Time stamp control register
bit 1.
7. Program the Time stamp high update and Time stamp low update registers with the
appropriate time value.
8. Set Time stamp control register bit 2 (Time stamp init).
9. The Time stamp counter starts operation as soon as it is initialized with the value
written in the Time stamp update register.
10. Enable the MAC receiver and transmitter for proper time stamping.
If time stamp operation is disabled by clearing bit 0 in the ETH_PTPTSCR register, the
above steps must be repeated to restart the time stamp operation.
876/995 Doc ID 13902 Rev 9