STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
USB on-the-go full-speed (OTG_FS)
OTG_FS reset register (OTG_FS_GRSTCTL)
Address offset: 0x10
Reset value: 0x2000 0000
The application uses this register to reset various hardware features inside the core.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AHBIDL
TXFNUM
Reserved
TXFFLSH
RXFFLSH
Reserved
FCRST
HSRST
CSRST
r rw rs rs rs rs rs
Bit 31 AHBIDL: AHB master idle
Indicates that the AHB master state machine is in the Idle condition.
Note: Accessible in both Device and Host modes.
Bits 30:11 Reserved
Bits 10:6 TXFNUM: TxFIFO number
This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not be
changed until the core clears the TxFIFO Flush bit.
● 00000:
– Non-periodic TxFIFO flush in Host mode
– Tx FIFO 0 flush in Device mode
● 00001:
– Periodic TxFIFO flush in Host mode
– TXFIFO 1 flush in device mode
● 00010: TXFIFO 2 flush in device mode
...
● 00101: TXFIFO 15 flush in device mode
● 10000: Flush all the transmit FIFOs in device or host mode.
Note: Accessible in both Device and Host modes.
Bit 5 TXFFLSH: TxFIFO flush
This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the
midst of a transaction.
The application must write this bit only after checking that the core is neither writing to the
TxFIFO nor reading from the TxFIFO. Verify using these registers:
Read—NAK Effective Interrupt ensures the core is not reading from the FIFO
Write—AHBIDL bit in OTG_FS_GRSTCTL ensures the core is not writing anything to the
FIFO.
Note: Accessible in both Device and Host modes.
Bit 4 RXFFLSH: RxFIFO flush
The application can flush the entire RxFIFO using this bit, but must first ensure that the core is
not in the middle of a transaction.
The application must only write to this bit after checking that the core is neither reading from the
RxFIFO nor writing to the RxFIFO.
The application must wait until the bit is cleared before performing any other operations. This bit
requires 8 clocks (slowest of PHY or AHB clock) to clear.
Note: Accessible in both Device and Host modes.
Doc ID 13902 Rev 9 729/995