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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

Secure digital input/output interface (SDIO)<br />

Control unit<br />

The control unit contains the power management functions <strong>and</strong> the clock divider for the<br />

memory card clock.<br />

There are three power phases:<br />

● power-off<br />

● power-up<br />

● power-on<br />

Figure 184. Control unit<br />

Control unit<br />

Power management<br />

Adapter<br />

registers<br />

Clock<br />

management<br />

SDIO_CK<br />

To comm<strong>and</strong> <strong>and</strong> data path<br />

ai14804<br />

The control unit is illustrated in Figure 184. It consists of a power management subunit <strong>and</strong><br />

a clock management subunit.<br />

The power management subunit disables the card bus output signals during the power-off<br />

<strong>and</strong> power-up phases.<br />

The clock management subunit generates <strong>and</strong> controls the SDIO_CK signal. The SDIO_CK<br />

output can use either the clock divide or the clock bypass mode. The clock output is inactive:<br />

●<br />

●<br />

●<br />

after reset<br />

during the power-off or power-up phases<br />

if the power saving mode is enabled <strong>and</strong> the card bus is in the Idle state (eight clock<br />

periods after both the comm<strong>and</strong> <strong>and</strong> data path subunits enter the Idle phase)<br />

Comm<strong>and</strong> path<br />

The comm<strong>and</strong> path unit sends comm<strong>and</strong>s to <strong>and</strong> receives responses from the cards.<br />

Doc ID 13902 Rev 9 461/995

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