STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Window watchdog (WWDG)
RM0008
18.4 How to program the watchdog timeout
Figure 160 shows the linear relationship between the 6-bit value to be loaded in the
watchdog counter (CNT) and the resulting timeout duration in milliseconds. This can be
used for a quick calculation without taking the timing variations into account. If more
precision is needed, use the formulae in Figure 160.
Warning:
When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
Figure 160. Window watchdog timing diagram
T[6:0] CNT downcounter
W[6:0]
3Fh
Refresh not allowed
T6 bit
Refresh window
time
Reset
The formula to calculate the timeout value is given by:
T = T 4096 2 WDGTB T5:0
+ 1
;ms
WWDG PCLK1
where:
T WWDG : WWDG timeout
T PCLK1 : APB1 clock period measured in ms
Min-max timeout value @36 MHz (PCLK1)
WDGTB Min timeout value Max timeout value
0 113 µs 7.28 ms
1 227 µs 14.56 ms
2 455 µs 29.12 ms
3 910 µs 58.25 ms
18.5 Debug mode
When the microcontroller enters debug mode (Cortex-M3 core halted), the WWDG counter
either continues to work normally or stops, depending on DBG_WWDG_STOP configuration
bit in DBG module. For more details, refer to Section 29.16.2: Debug support for timers,
watchdog, bxCAN and I 2 C.
406/995 Doc ID 13902 Rev 9