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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Low-, medium- <strong>and</strong> high-density reset <strong>and</strong> clock control (RCC)<br />

RM0008<br />

Bit 23 USBRST: USB reset<br />

Set <strong>and</strong> cleared by software.<br />

0: No effect<br />

1: Reset USB<br />

Bit 22 I2C2RST: I2C 2 reset<br />

Set <strong>and</strong> cleared by software.<br />

0: No effect<br />

1: Reset I2C 2<br />

Bit 21 I2C1RST: I2C 1 reset<br />

Set <strong>and</strong> cleared by software.<br />

0: No effect<br />

1: Reset I2C 1<br />

Bit 20 UART5RST: USART 5 reset<br />

Set <strong>and</strong> cleared by software.<br />

0: No effect<br />

1: Reset USART 5<br />

Bit 19 UART4RST: USART 4 reset<br />

Set <strong>and</strong> cleared by software.<br />

0: No effect<br />

1: Reset USART 4<br />

Bit 18 USART3RST: USART 3 reset<br />

Set <strong>and</strong> cleared by software.<br />

0: No effect<br />

1: Reset USART 3<br />

Bit 17 USART2RST: USART 2 reset<br />

Set <strong>and</strong> cleared by software.<br />

0: No effect<br />

1: Reset USART 2<br />

Bits 16 Reserved, always read as 0.<br />

Bit 15 SPI3RST: SPI 3 reset<br />

Set <strong>and</strong> cleared by software.<br />

0: No effect<br />

1: Reset SPI 3<br />

Bit 14 SPI2RST: SPI 2 reset<br />

Set <strong>and</strong> cleared by software.<br />

0: No effect<br />

1: Reset SPI 2<br />

Bits 13:12 Reserved, always read as 0.<br />

Bit 11 WWDGRST: Window watchdog reset<br />

Set <strong>and</strong> cleared by software.<br />

0: No effect<br />

1: Reset window watchdog<br />

Bits 10:6 Reserved, always read as 0.<br />

92/995 Doc ID 13902 Rev 9

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