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Controller area network (bxCAN) RM0008 Filter bank i register x (CAN_FiRx) (i=0..27 in connectivity line devices,, x=1, 2) Address offsets: 0x240..0x31C Reset value: undefined Note: In connectivity line devices there are 28 filter banks, i=0 .. 27, in other devices there are 14 filter banks i = 0 ..13. Each filter bank i is composed of two 32-bit registers, CAN_FiR[2:1]. This register can only be modified when the FACTx bit of the CAN_FAxR register is cleared or when the FINIT bit of the CAN_FMR register is set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FB15 FB14 FB13 FB12 FB11 FB10 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 FB0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw In all configurations: Bits 31:0 FB[31:0]: Filter bits Identifier Each bit of the register specifies the level of the corresponding bit of the expected identifier. 0: Dominant bit is expected 1: Recessive bit is expected Mask Each bit of the register specifies whether the bit of the associated identifier register must match with the corresponding bit of the expected identifier or not. 0: Don’t care, the bit is not used for the comparison 1: Must match, the bit of the incoming identifier must have the same level has specified in the corresponding identifier register of the filter. Note: Depending on the scale and mode configuration of the filter the function of each register can differ. For the filter mapping, functions description and mask registers association, refer to Section 22.7.4: Identifier filtering on page 552. A Mask/Identifier register in mask mode has the same bit mapping as in identifier list mode. For the register mapping/addresses of the filter banks please refer to the Table 164 on page 583. 582/995 Doc ID 13902 Rev 9
RM0008 Controller area network (bxCAN) 22.9.5 bxCAN register map Refer to Table 1 on page 41 for the register boundary addresses. In connectivity line devices, the registers from offset 0x200 to 31C are present only in CAN1. Table 164. bxCAN register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 CAN_MCR Reserved DBF RESET Reserved TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ Reset value 1 0 0 0 0 0 0 0 1 0 0x004 CAN_MSR Reserved RX SAMP RXM TXM Reserved SLAKI WKUI ERRI SLAK INAK Reset value 1 1 0 0 0 0 0 1 0 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020- 0x17F CAN_TSR LOW[2:0] TME[2:0] CODE[1:0] ABRQ2 Reserved TERR2 ALST2 TXOK2 RQCP2 ABRQ1 Reserved TERR1 ALST1 TXOK1 RQCP1 ABRQ0 Reserved TERR0 ALST0 TXOK0 RQCP0 Reset value 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_RF0R Reserved RFOM0 FOVR0 FULL0 Reset value 0 0 0 0 0 CAN_RF1R Reserved RFOM1 FOVR1 FULL1 Reset value 0 0 0 0 0 CAN_IER Reserved SLKIE WKUIE ERRIE Reserved LECIE BOFIE EPVIE EWGIE Reserved Reserved Reserved FMP0[1:0] FMP1[1:0] FOVIE1 FFIE1 FMPIE1 FOVIE0 FFIE0 FMPIE0 TMEIE Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_ESR REC[7:0] TEC[7:0] Reserved LEC[2:0] Reserved BOFF EPVF EWGF Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_BTR SILM LBKM Reserved SJW[1:0] Reserved TS2[2:0] TS1[3:0] BRP[9:0] Reserved Reset value 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 Reserved 0x180 CAN_TI0R STID[10:0]/EXID[28:18] EXID[17:0] IDE RTR TXRQ Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0x184 CAN_TDT0R TIME[15:0] Reserved TGT Reserved DLC[3:0] Reset value x x x x x x x x x x x x x x x x x x x x x 0x188 CAN_TDL0R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x18C CAN_TDH0R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x190 CAN_TI1R STID[10:0]/EXID[28:18] EXID[17:0] IDE RTR TXRQ Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 Doc ID 13902 Rev 9 583/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Ethernet (ETH): media access
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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