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DMA controller (DMA) RM0008 10.4.7 DMA register map Table 59. Offset The following table gives the DMA register map and the reset values. DMA register map and reset values Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 0x004 DMA_ISR Reserved TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5 TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_IFCR Reserved CTEIF7 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x008 DMA_CCR1 Reserved MEM2MEM PL [1:0] M SIZE [1:0] PSIZ E [1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00C DMA_CNDTR1 NDT[15:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x010 0x014 0x018 DMA_CPAR1 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR1 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 DMA_CCR2 Reserved MEM2MEM PL [1:0] M SIZE [1:0] PSIZ E [1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CNDTR2 NDT[15:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CPAR2 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR2 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved DMA_CCR3 Reserved MEM2MEM PL [1:0] M SIZE [1:0] PSIZ E [1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CNDTR3 NDT[15:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CPAR3 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR3 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved DMA_CCR4 Reserved MEM2MEM PL [1:0] M SIZE [1:0] PSIZ E [1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CNDTR4 NDT[15:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 196/995 Doc ID 13902 Rev 9
RM0008 DMA controller (DMA) Table 59. DMA register map and reset values (continued) Offset Register 0x04C 0x050 0x054 0x058 DMA_CPAR4 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR4 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved DMA_CCR5 Reserved MEM2MEM PL [1:0] M SIZE [1:0] PSIZ E [1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x05C DMA_CNDTR5 NDT[15:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x060 0x064 0x068 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMA_CPAR5 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR5 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0x06C 0x070 0x074 0x078 0x07C 0x080 0x084 0x088 0x08C 0x090 DMA_CCR6 Reserved MEM2MEM PL [1:0] M SIZE [1:0] PSIZ E [1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CNDTR6 NDT[15:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CPAR6 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR6 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved DMA_CCR7 Reserved MEM2MEM PL [1:0] M SIZE [1:0] PSIZ E [1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CNDTR7 NDT[15:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CPAR7 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR7 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Refer to Table 1 on page 41 for the register boundary addresses. Doc ID 13902 Rev 9 197/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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