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Advanced-control timers (TIM1&TIM8) RM0008 Table 73. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states (1) MOE bit OSSI bit 1 X 0 OSSR bit CCxE bit CCxNE bit 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 OCx output state Output Disabled (not driven by the timer) OCx=0, OCx_EN=0 Output Disabled (not driven by the timer) OCx=0, OCx_EN=0 OCxREF + Polarity OCx=OCxREF xor CCxP, OCx_EN=1 OCREF + Polarity + deadtime OCx_EN=1 Output Disabled (not driven by the timer) OCx=CCxP, OCx_EN=0 Off-State (output enabled with inactive state) OCx=CCxP, OCx_EN=1 OCxREF + Polarity OCx=OCxREF xor CCxP, OCx_EN=1 OCREF + Polarity + deadtime OCx_EN=1 OCxN output state Output Disabled (not driven by the timer) OCxN=0, OCxN_EN=0 OCxREF + Polarity OCxN=OCxREF xor CCxNP, OCxN_EN=1 Output Disabled (not driven by the timer) OCxN=0, OCxN_EN=0 Complementary to OCREF (not OCREF) + Polarity + dead-time OCxN_EN=1 Output Disabled (not driven by the timer) OCxN=CCxNP, OCxN_EN=0 OCxREF + Polarity OCxN=OCxREF xor CCxNP, OCxN_EN=1 Off-State (output enabled with inactive state) OCxN=CCxNP, OCxN_EN=1 Complementary to OCREF (not OCREF) + Polarity + dead-time OCxN_EN=1 0 0 0 Output Disabled (not driven by the timer) 0 0 1 Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP, 0 1 0 OCxN_EN=0 Then if the clock is present: OCx=OISx and OCxN=OISxN 0 1 1 after a dead-time, assuming that OISx and OISxN do not 1 X 0 0 correspond to OCX and OCxN both in active state. 1 0 1 Off-State (output enabled with inactive state) 1 1 0 Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP, OCxN_EN=1 Then if the clock is present: OCx=OISx and OCxN=OISxN 1 1 1 after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state 1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared. Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO and AFIO registers. 310/995 Doc ID 13902 Rev 9
RM0008 Advanced-control timers (TIM1&TIM8) 13.4.10 TIM1&TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Counter value 13.4.11 TIM1&TIM8 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f CK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). 13.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 13.3.1: Time-base unit on page 256 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Doc ID 13902 Rev 9 311/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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