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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Flexible static memory controller (FSMC)<br />

RM0008<br />

Figure 174. Synchronous multiplexed write mode - PSRAM (CRAM)<br />

Memory transaction = burst of 4 half words<br />

HCLK<br />

CLK<br />

A[25:16]<br />

addr[25:16]<br />

NEx<br />

NOE<br />

Hi-Z<br />

NWE<br />

NADV<br />

NWAIT<br />

(WAITCFG = 0)<br />

DATALAT CLK cycles<br />

inserted wait state<br />

A/D[15:0]<br />

Addr[15:0] data data data data<br />

1 CLK<br />

cycle<br />

1 CLK<br />

cycle<br />

ai14731c<br />

1. Memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.<br />

2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.<br />

434/995 Doc ID 13902 Rev 9

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