STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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USB on-the-go full-speed (OTG_FS) RM0008 ● periodic request queue depth is smaller than the periodic transfers scheduled in a microframe, a frame overrun condition occurs. Handling babble conditions OTG_FS controller handles two cases of babble: packet babble and port babble. Packet babble occurs if the device sends more data than the maximum packet size for the channel. Port babble occurs if the core continues to receive data from the device at EOF2 (the end of frame 2, which is very close to SOF). When OTG_FS controller detects a packet babble, it stops writing data into the Rx buffer and waits for the end of packet (EOP). When it detects an EOP, it flushes already written data in the Rx buffer and generates a Babble interrupt to the application. When OTG_FS controller detects a port babble, it flushes the RxFIFO and disables the port. The core then generates a Port disabled interrupt (HPRTINT in OTG_FS_GINTSTS, PENCHNG in OTG_FS_HPRT). On receiving this interrupt, the application must determine that this is not due to an overcurrent condition (another cause of the Port Disabled interrupt) by checking POCA in OTG_FS_HPRT, then perform a soft reset. The core does not send any more tokens after it has detected a port babble condition. 26.15.5 Device programming model Endpoint initialization on USB reset 1. Set the NAK bit for all OUT endpoints – SNAK = 1 in OTG_FS_DOEPCTLx (for all OUT endpoints) 2. Unmask the following interrupt bits – INEP0 = 1 in OTG_FS_DAINTMSK (control 0 IN endpoint) – OUTEP0 = 1 in OTG_FS_DAINTMSK (control 0 OUT endpoint) – STUP = 1 in DOEPMSK – XFRC = 1 in DOEPMSK – XFRC = 1 in DIEPMSK – TOC = 1 in DIEPMSK 3. Set up the Data FIFO RAM for each of the FIFOs – Program the OTG_FS_GRXFSIZ register, to be able to receive control OUT data and setup data. If thresholding is not enabled, at a minimum, this must be equal to 1 max packet size of control endpoint 0 + 2 DWORDs (for the status of the control OUT data packet) + 10 DWORDs (for setup packets). – Program the OTG_FS_GNPTXFSIZ register (depending on the FIFO number chosen) to be able to transmit control IN data. At a minimum, this must be equal to 1 max packet size of control endpoint 0. 4. Program the following fields in the endpoint-specific registers for control OUT endpoint 0 to receive a SETUP packet – STUPCNT = 3 in OTG_FS_DOEPTSIZ0 (to receive up to 3 back-to-back SETUP packets) At this point, all initialization required to receive SETUP packets is done. 810/995 Doc ID 13902 Rev 9
RM0008 USB on-the-go full-speed (OTG_FS) Endpoint initialization on enumeration completion 1. On the Enumeration Done interrupt (ENUMDNE in OTG_FS_GINTSTS), read the OTG_FS_DSTS register to determine the enumeration speed. 2. Program the MPSIZ field in OTG_FS_DIEPCTL0 to set the maximum packet size. This step configures control endpoint 0. The maximum packet size for a control endpoint depends on the enumeration speed. At this point, the device is ready to receive SOF packets and is configured to perform control transfers on control endpoint 0. Endpoint initialization on SetAddress command This section describes what the application must do when it receives a SetAddress command in a SETUP packet. 1. Program the OTG_FS_DCFG register with the device address received in the SetAddress command 1. Program the core to send out a status IN packet Endpoint initialization on SetConfiguration/SetInterface command This section describes what the application must do when it receives a SetConfiguration or SetInterface command in a SETUP packet. 1. When a SetConfiguration command is received, the application must program the endpoint registers to configure them with the characteristics of the valid endpoints in the new configuration. 2. When a SetInterface command is received, the application must program the endpoint registers of the endpoints affected by this command. 3. Some endpoints that were active in the prior configuration or alternate setting are not valid in the new configuration or alternate setting. These invalid endpoints must be deactivated. 4. Unmask the interrupt for each active endpoint and mask the interrupts for all inactive endpoints in the OTG_FS_DAINTMSK register. 5. Set up the Data FIFO RAM for each FIFO. 6. After all required endpoints are configured; the application must program the core to send a status IN packet. At this point, the device core is configured to receive and transmit any type of data packet. Endpoint activation This section describes the steps required to activate a device endpoint or to configure an existing device endpoint to a new type. Doc ID 13902 Rev 9 811/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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