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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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USB on-the-go full-speed (OTG_FS)<br />

RM0008<br />

●<br />

periodic request queue depth is smaller than the periodic transfers scheduled in a<br />

microframe, a frame overrun condition occurs.<br />

H<strong>and</strong>ling babble conditions<br />

OTG_FS controller h<strong>and</strong>les two cases of babble: packet babble <strong>and</strong> port babble.<br />

Packet babble occurs if the device sends more data than the maximum packet size for<br />

the channel. Port babble occurs if the core continues to receive data from the device at<br />

EOF2 (the end of frame 2, which is very close to SOF).<br />

When OTG_FS controller detects a packet babble, it stops writing data into the Rx<br />

buffer <strong>and</strong> waits for the end of packet (EOP). When it detects an EOP, it flushes already<br />

written data in the Rx buffer <strong>and</strong> generates a Babble interrupt to the application.<br />

When OTG_FS controller detects a port babble, it flushes the RxFIFO <strong>and</strong> disables the<br />

port. The core then generates a Port disabled interrupt (HPRTINT in<br />

OTG_FS_GINTSTS, PENCHNG in OTG_FS_HPRT). On receiving this interrupt, the<br />

application must determine that this is not due to an overcurrent condition (another<br />

cause of the Port Disabled interrupt) by checking POCA in OTG_FS_HPRT, then<br />

perform a soft reset. The core does not send any more tokens after it has detected a<br />

port babble condition.<br />

26.15.5 Device programming model<br />

Endpoint initialization on USB reset<br />

1. Set the NAK bit for all OUT endpoints<br />

– SNAK = 1 in OTG_FS_DOEPCTLx (for all OUT endpoints)<br />

2. Unmask the following interrupt bits<br />

– INEP0 = 1 in OTG_FS_DAINTMSK (control 0 IN endpoint)<br />

– OUTEP0 = 1 in OTG_FS_DAINTMSK (control 0 OUT endpoint)<br />

– STUP = 1 in DOEPMSK<br />

– XFRC = 1 in DOEPMSK<br />

– XFRC = 1 in DIEPMSK<br />

– TOC = 1 in DIEPMSK<br />

3. Set up the Data FIFO RAM for each of the FIFOs<br />

– Program the OTG_FS_GRXFSIZ register, to be able to receive control OUT data<br />

<strong>and</strong> setup data. If thresholding is not enabled, at a minimum, this must be equal to<br />

1 max packet size of control endpoint 0 + 2 DWORDs (for the status of the control<br />

OUT data packet) + 10 DWORDs (for setup packets).<br />

– Program the OTG_FS_GNPTXFSIZ register (depending on the FIFO number<br />

chosen) to be able to transmit control IN data. At a minimum, this must be equal to<br />

1 max packet size of control endpoint 0.<br />

4. Program the following fields in the endpoint-specific registers for control OUT endpoint<br />

0 to receive a SETUP packet<br />

– STUPCNT = 3 in OTG_FS_DOEPTSIZ0 (to receive up to 3 back-to-back SETUP<br />

packets)<br />

At this point, all initialization required to receive SETUP packets is done.<br />

810/995 Doc ID 13902 Rev 9

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