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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

Ethernet (ETH): media access control (MAC) with DMA controller<br />

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Option to filter all error frames on reception <strong>and</strong> not forward them to the application in<br />

Store-<strong>and</strong>-Forward mode<br />

Option to forward under-sized good frames<br />

Supports statistics by generating pulses for frames dropped or corrupted (due to<br />

overflow) in the Receive FIFO<br />

Supports Store <strong>and</strong> Forward mechanism for transmission to the MAC core<br />

Automatic generation of PAUSE frame control or back pressure signal to the MAC core<br />

based on Receive FIFO-fill (threshold configurable) level<br />

H<strong>and</strong>les automatic retransmission of Collision frames for transmission<br />

Discards frames on late collision, excessive collisions, excessive deferral <strong>and</strong> underrun<br />

conditions<br />

Software control to flush Tx FIFO<br />

Calculates <strong>and</strong> inserts IPv4 header checksum <strong>and</strong> TCP, UDP, or ICMP checksum in<br />

frames transmitted in Store-<strong>and</strong>-Forward mode<br />

Supports internal loopback on the MII for debugging<br />

27.2.2 DMA features<br />

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Supports all AHB burst types in the AHB Slave Interface<br />

Software can select the type of AHB burst (fixed or indefinite burst) in the AHB Master<br />

interface.<br />

Option to select address-aligned bursts from AHB master port<br />

Optimization for packet-oriented DMA transfers with frame delimiters<br />

Byte-aligned addressing for data buffer support<br />

Dual-buffer (ring) or linked-list (chained) descriptor chaining<br />

Descriptor architecture, allowing large blocks of data transfer with minimum CPU<br />

intervention;<br />

each descriptor can transfer up to 8 KB of data<br />

Comprehensive status reporting for normal operation <strong>and</strong> transfers with errors<br />

Individual programmable burst size for Transmit <strong>and</strong> Receive DMA Engines for optimal<br />

host bus utilization<br />

Programmable interrupt options for different operational conditions<br />

Per-frame Transmit/Receive complete interrupt control<br />

Round-robin or fixed-priority arbitration between Receive <strong>and</strong> Transmit engines<br />

Start/Stop modes<br />

Current Tx/Rx Buffer pointer as status registers<br />

Current Tx/Rx Descriptor pointer as status registers<br />

27.2.3 PTP features<br />

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Received <strong>and</strong> transmitted frames time stamping<br />

Coarse <strong>and</strong> fine correction methods<br />

Trigger interrupt when system time becomes greater than target time<br />

Pulse per second output (product alternate function output)<br />

Doc ID 13902 Rev 9 839/995

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