STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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USB on-the-go full-speed (OTG_FS) RM0008 Figure 271. Receive FIFO read task Start No RXFLVL interrupt Yes Unmask RXFLVL interrupt Mask RXFLVL interrupt Unmask RXFLVL interrupt Read the received packet from the Receive FIFO Read OTG_FS_GRXSTSP PKTSTS 0b0010 No Yes Yes BCNT > 0 No ai15674 ● ● Bulk and control OUT/SETUP transactions A typical bulk or control OUT/SETUP pipelined transaction-level operation is shown in Figure 272. See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control SETUP transaction operates in the same way but has only one packet. The assumptions are: – The application is attempting to send two maximum-packet-size packets (transfer size = 1, 024 bytes). – The non-periodic transmit FIFO can hold two packets (128 KB for FS). – The non-periodic request queue depth = 4. Normal bulk and control OUT/SETUP operations The sequence of operations in Figure 272 (channel 1) is as follows: a) Initialize channel 1 b) Write the first packet for channel 1 c) Along with the last DWORD write, the core writes an entry to the non-periodic request queue d) As soon as the non-periodic queue becomes non-empty, the core attempts to send an OUT token in the current frame e) Write the second (last) packet for channel 1 f) The core generates the XFRC interrupt as soon as the last transaction is completed successfully g) In response to the XFRC interrupt, de-allocate the channel for other transfers h) Handling non-ACK responses 796/995 Doc ID 13902 Rev 9
RM0008 USB on-the-go full-speed (OTG_FS) Figure 272. Normal bulk/control OUT/SETUP and bulk/control IN transactions init_reg(ch_2) set_ch_en (ch_2) set_ch_en (ch_2) 1 1 2 2 5 Application init_reg(ch_1) write_tx_fifo (ch_1) write_tx_fifo (ch_1) AHB 1 MPS 1 MPS 3 Host 4 ch_1 ch_2 ch_1 USB Non-Periodic Request Queue Assume that this queue can hold 4 entries. OUT Device ch_2 DATA0 MPS set_ch_en (ch_2) 3 ACK IN 5 RXFLVL interrupt 4 DATA0 read_rx_sts read_rx_fifo 1 MPS ch_1 ch_2 ACK OUT set_ch_en (ch_2) ch_2 ch_2 DATA1 MPS 7 De-allocate (ch_1) XFRC interrupt 6 ACK IN DATA1 RXFLVL interrupt read_rx_stsre ad_rx_fifo 1 MPS 6 ACK read_rx_sts Disable (ch_2) 7 9 RXFLVL interrupt XFRC interrupt RXFLVL interrupt read_rx_sts 11 10 CHH interrupt r 8 ch_2 De-allocate (ch_2) 13 12 ai15675 ● The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions in Slave mode is shown in the following code samples. Interrupt service routine for bulk/control OUT/SETUP and bulk/control IN transactions a) Bulk/Control OUT/SETUP Unmask (NAK/TXERR/STALL/XFRC) if (XFRC) { Reset Error Count Mask ACK De-allocate Channel Doc ID 13902 Rev 9 797/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) transfe
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RM0008 DMA controller (DMA) not sup
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Pre
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Device electronic signature
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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