STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Memory and bus architecture RM0008 DCode bus This bus connects the DCode bus (literal load and debug access) of the Cortex-M3 core to the Flash memory Data interface. System bus This bus connects the system bus of the Cortex-M3 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA. DMA bus This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of CPU DCode and DMA to SRAM, Flash memory and peripherals. BusMatrix The BusMatrix manages the access arbitration between the core system bus and the DMA master bus. The arbitration uses a Round Robin algorithm. In connectivity line devices, the BusMatrix is composed of five masters (CPU DCode, System bus, Ethernet DMA, DMA1 and DMA2 bus) and three slaves (FLITF, SRAM and AHB2APB bridges). In other devices, the BusMatrix is composed of four masters (CPU DCode, System bus, DMA1 bus and DMA2 bus) and four slaves (FLITF, SRAM, FSMC and AHB2APB bridges). AHB peripherals are connected on system bus through a BusMatrix to allow DMA access. AHB/APB bridges (APB) Note: The two AHB/APB bridges provide full synchronous connections between the AHB and the 2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz depending on the device). Refer to Table 1 on page 41 for the address mapping of the peripherals connected to each bridge. After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF). Before using a peripheral you have to enable its clock in the RCC_AHBENR, RCC_APB2ENR or RCC_APB1ENR register. When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector. 2.2 Memory organization Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant. For the detailed mapping of peripheral registers, please refer to the related chapters. The addressable memory space is divided into 8 main blocks, each of 512 MB. All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”). Refer to the Memory map figure in the corresponding product datasheet. 40/995 Doc ID 13902 Rev 9
RM0008 Memory and bus architecture 2.3 Memory map Table 1. See the datasheet corresponding to your device for a comprehensive diagram of the memory map. Table 1 gives the boundary addresses of the peripherals available in all STM32F10xxx devices. Register boundary addresses Boundary address Peripheral Bus Register map 0x5000 0000 - 0x5000 03FF 0x4003 0000 - 0x4FFF FFFF USB OTG FS Reserved AHB Section 26.14.6 on page 778 0x4002 8000 - 0x4002 9FFF Ethernet Section 27.8.5 on page 946 0x4002 3400 - 0x4002 7FFF Reserved 0x4002 3000 - 0x4002 33FF CRC Section 3.4.4 on page 52 0x4002 2000 - 0x4002 23FF 0x4002 1400 - 0x4002 1FFF Flash memory interface Reserved 0x4002 1000 - 0x4002 13FF Reset and clock control RCC Section 6.3.11 on page 102 AHB 0x4002 0800 - 0x4002 0FFF Reserved 0x4002 0400 - 0x4002 07FF DMA2 Section 10.4.7 on page 196 0x4002 0000 - 0x4002 03FF DMA1 Section 10.4.7 on page 196 0x4001 8400 - 0x4001 7FFF Reserved 0x4001 8000 - 0x4001 83FF SDIO Section 20.9.16 on page 510 0x4001 4000 - 0x4001 7FFF Reserved 0x4001 3C00 - 0x4001 3FFF ADC3 Section 11.12.15 on page 231 0x4001 3800 - 0x4001 3BFF USART1 Section 25.6.8 on page 693 0x4001 3400 - 0x4001 37FF TIM8 timer Section 13.4.21 on page 317 0x4001 3000 - 0x4001 33FF SPI1 Section 23.5 on page 614 0x4001 2C00 - 0x4001 2FFF TIM1 timer Section 13.4.21 on page 317 0x4001 2800 - 0x4001 2BFF ADC2 Section 11.12.15 on page 231 0x4001 2400 - 0x4001 27FF ADC1 Section 11.12.15 on page 231 0x4001 2000 - 0x4001 23FF GPIO Port G APB2 Section 8.5 on page 167 0x4001 1C00 - 0x4001 1FFF GPIO Port F Section 8.5 on page 167 0x4001 1800 - 0x4001 1BFF GPIO Port E Section 8.5 on page 167 0x4001 1400 - 0x4001 17FF GPIO Port D Section 8.5 on page 167 0x4001 1000 - 0x4001 13FF GPIO Port C Section 8.5 on page 167 0x4001 0C00 - 0x4001 0FFF GPIO Port B Section 8.5 on page 167 0x4001 0800 - 0x4001 0BFF GPIO Port A Section 8.5 on page 167 0x4001 0400 - 0x4001 07FF EXTI Section 9.3.7 on page 181 0x4001 0000 - 0x4001 03FF AFIO Section 8.5 on page 167 Doc ID 13902 Rev 9 41/995
Page 1 and 2: RM0008 Reference manual STM32F101xx
Page 3 and 4: RM0008 Contents 4.3.1 Slowing down
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Page 9 and 10: RM0008 Contents 12.3.2 DAC output b
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Debug support (DBG) Figure 3
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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