STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Advanced-control timers (TIM1&TIM8)
RM0008
Figure 67.
Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
0034 0035
0036 0035
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow
Figure 68.
Counter timing diagram, internal clock divided by N
CK_PSC
Timer clock = CK_CNT
Counter register 20 1F
01
00
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 69.
Counter timing diagram, update event with ARPE=1 (counter underflow)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
06
05 04 03 02 01 00 01 02 03 04 05 06 07
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register FD 36
Write a new value in TIMx_ARR
Auto-reload active register FD 36
264/995 Doc ID 13902 Rev 9