STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Flexible static memory controller (FSMC)
RM0008
Mode 1 - SRAM/CRAM
Figure 162. Mode1 read accesses
Memory transaction
A[25:0]
NBL[1:0]
NEx
NOE
NWE
High
D[15:0]
data driven
by memory
(ADDSET +1) (DATAST + 1)
HCLK cycles HCLK cycles
2 HCLK
cycles
Data sampled
Data strobe
ai14720c
Mode1 write accessesThe one HCLK cycle at the end of the write transaction helps
Memory transaction
A[25:0]
NBL[1:0]
NEx
NOE
NWE
1HCLK
D[15:0]
data driven by FSMC
(ADDSET +1) (DATAST + 1)
HCLK cycles HCLK cycles
ai14721c
guarantee the address and data hold time after the NWE rising edge. Due to the presence
of this one HCLK cycle, the DATAST value must be greater than zero (DATAST > 0).
418/995 Doc ID 13902 Rev 9