STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Serial peripheral interface (SPI)
23.4.3 Clock generator
The I 2 S bitrate determines the dataflow on the I 2 S data line and the I 2 S clock signal
frequency.
I 2 S bitrate = number of bits per channel × number of channels × sampling audio frequency
For a 16-bit audio, left and right channel, the I 2 S bitrate is calculated as follows:
I 2 S bitrate = 16 × 2 × F S
It will be: I 2 S bitrate = 32 x 2 x F S if the packet length is 32-bit wide.
Figure 229. Audio sampling frequency definition
16-bit or 32-bit Left channel
16-bit or 32-bit Right channel
32-bits or 64-bits
sampling point
F S
sampling point
F S : Audio sampling frequency
When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
Figure 230. I 2 S clock generator architecture
MCK
I2SxCLK
8-bit Linear
Divider +
reshaping stage
Divider by 4
Div2
0
1
0
1
CK
MCKOE
MCKOE
ODD
I2SDIV[7:0]
I2SMOD
CHLEN
1. Where x could be 2 or 3.
Figure 229 presents the communication clock architecture. the I2SxCLK source is the
system clock (provided by the HSI, the HSE or the PLL and sourcing the AHB clock). For
connectivity line devices, the I2SxCLK source can be either SYSCLK or the PLL3 VCO
clock in order to have maximum accuracy. This selection is made using the I2S2SRC and
I2S3SRC bits in the RCC_CFGR2 register.
The audio sampling frequency may be 96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 22.05 kHz,
16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to reach the
desired frequency, the linear divider needs to be programmed according to the formulas
below:
Doc ID 13902 Rev 9 607/995