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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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USB on-the-go full-speed (OTG_FS)<br />

RM0008<br />

OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)<br />

Address offset: 0x900<br />

Reset value: 0x0000 0000<br />

This section describes the device control IN endpoint 0 control register. Nonzero control<br />

endpoints use registers for endpoints 1–15.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

EPENA<br />

EPDIS<br />

Reserved<br />

SNAK<br />

CNAK<br />

TXFNUM<br />

STALL<br />

Reserved<br />

EPTYP<br />

NAKSTS<br />

Reserved<br />

USBAEP<br />

MPSIZ<br />

Reserved<br />

rs r w w rw rw rw rw rs r r r r rw rw<br />

Bit 31 EPENA: Endpoint enable<br />

The application sets this bit to start transmitting data on the endpoint 0.<br />

The core clears this bit before setting any of the following interrupts on this endpoint:<br />

– Endpoint disabled<br />

– Transfer completed<br />

Bit 30 EPDIS: Endpoint disable<br />

The application sets this bit to stop transmitting data on an endpoint, even before the transfer<br />

for that endpoint is complete. The application must wait for the Endpoint disabled interrupt<br />

before treating the endpoint as disabled. The core clears this bit before setting the Endpoint<br />

disabled interrupt. The application must set this bit only if Endpoint enable is already set for<br />

this endpoint.<br />

Bits 29:28 Reserved<br />

Bit 27 SNAK: Set NAK<br />

A write to this bit sets the NAK bit for the endpoint.<br />

Using this bit, the application can control the transmission of NAK h<strong>and</strong>shakes on an endpoint.<br />

The core can also set this bit for an endpoint after a SETUP packet is received on that<br />

endpoint.<br />

Bit 26 CNAK: Clear NAK<br />

A write to this bit clears the NAK bit for the endpoint.<br />

Bits 25:22 TXFNUM: TxFIFO number<br />

This value is set to the FIFO number that is assigned to IN endpoint 0.<br />

Bit 21 STALL: STALL h<strong>and</strong>shake<br />

The application can only set this bit, <strong>and</strong> the core clears it when a SETUP token is received for<br />

this endpoint. If a NAK bit, a Global IN NAK or Global OUT NAK is set along with this bit, the<br />

STALL bit takes priority.<br />

Bit 20 Reserved<br />

Bits 19:18 EPTYP: Endpoint type<br />

Hardcoded to ‘00’ for control.<br />

762/995 Doc ID 13902 Rev 9

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