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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

Interrupts <strong>and</strong> events<br />

9 Interrupts <strong>and</strong> events<br />

Low-density devices are <strong>STM32F101xx</strong>, <strong>STM32F102xx</strong> <strong>and</strong> <strong>STM32F103xx</strong><br />

microcontrollers where the Flash memory density ranges between 16 <strong>and</strong> 32 Kbytes.<br />

Medium-density devices are <strong>STM32F101xx</strong>, <strong>STM32F102xx</strong> <strong>and</strong> <strong>STM32F103xx</strong><br />

microcontrollers where the Flash memory density ranges between 64 <strong>and</strong> 128 Kbytes.<br />

High-density devices are <strong>STM32F101xx</strong> <strong>and</strong> <strong>STM32F103xx</strong> microcontrollers where the<br />

Flash memory density ranges between 256 <strong>and</strong> 512 Kbytes.<br />

Connectivity line devices are <strong>STM32F105xx</strong> <strong>and</strong> STM32F107xx microcontrollers.<br />

This Section applies to the whole STM32F10xxx family, unless otherwise specified.<br />

9.1 Nested vectored interrupt controller (NVIC)<br />

Features<br />

●<br />

●<br />

●<br />

●<br />

68 maskable interrupt channels (not including the 16 interrupt lines of Cortex-M3)<br />

16 programmable priority levels (4 bits of interrupt priority are used)<br />

Low-latency exception <strong>and</strong> interrupt h<strong>and</strong>ling<br />

Power management control<br />

● Implementation of System Control Registers<br />

The NVIC <strong>and</strong> the processor core interface are closely coupled, which enables low latency<br />

interrupt processing <strong>and</strong> efficient processing of late arriving interrupts.<br />

All interrupts including the core exceptions are managed by the NVIC. For more information<br />

on exceptions <strong>and</strong> NVIC programming see Chap 5 Exceptions & Chap 8 Nested Vectored<br />

Interrupt Controller of the ARM Cortex-M3 Technical Reference Manual.<br />

9.1.1 SysTick calibration value register<br />

The SysTick calibration value is fixed to 9000, which gives a reference time base of 1 ms<br />

with the SysTick clock set to 9 MHz (max HCLK/8).<br />

9.1.2 Interrupt <strong>and</strong> exception vectors<br />

Table 52 <strong>and</strong> Table 53 are the vector tables for connectivity line <strong>and</strong> other STM32F10xxx<br />

devices, respectively.<br />

Table 52.<br />

Vector table for connectivity line devices<br />

Position<br />

Priority<br />

Type of<br />

priority<br />

Acronym Description Address<br />

- - - Reserved 0x0000_0000<br />

-3 fixed Reset Reset 0x0000_0004<br />

-2 fixed NMI<br />

Non maskable interrupt. The RCC<br />

Clock Security System (CSS) is<br />

linked to the NMI vector.<br />

0x0000_0008<br />

Doc ID 13902 Rev 9 169/995

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