STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
USB on-the-go full-speed (OTG_FS)
Soft disconnect
The powered state can be exited by software with the soft disconnect feature. The DP pullup
resistor is removed by setting the soft disconnect bit in the device control register (SDIS
bit in OTG_FS_DCTL), causing a device disconnect detection interrupt on the host side
even though the USB cable was not really removed from the host port.
Default state
In the Default state the OTG_FS expects to recieve a SET_ADDRESS command from the
host. No other USB operation is possible. When a valid SET_ADDRESS command is
decoded on the USB, the application writes the corresponding number into the device
address field in the device configuration register (DAD bit in OTG_FS_DCFG). The OTG_FS
then enters the address state and is ready to answer host transactions at the configured
USB address.
Suspended state
The OTG_FS peripheral constantly monitors the USB activity. After counting 3 ms of USB
idleness, the early suspend interrupt (ESUSP bit in OTG_FS_GINTSTS) is issued, and
confirmed 3 ms later, if appropriate, by the suspend interrupt (USBSUSP bit in
OTG_FS_GINTSTS). The device suspend bit is then automatically set in the device status
register (SUSPSTS bit in OTG_FS_DSTS) and the OTG_FS enters the suspended state.
The suspended state may optionally be exited by the device itself. In this case the
application sets the remote wakeup signaling bit in the device control register (WKUPINT bit
in OTG_FS_DCTL) and clears it after 1 to 15 ms.
When a resume signaling is detected from the host, the resume interrupt (RWUSIG bit in
OTG_FS_GINTSTS) is generated and the device suspend bit is automatically cleared.
26.5.3 Peripheral endpoints
The OTG_FS core instantiates the following USB endpoints:
● Control endpoint 0
– is bidirectional and handles control messages only
– has a separate set of registers to handle in and out transactions
– has proper control (DIEPCTL0/DOEPCTL0), transfer configuration
(DIEPTSIZ0/DIEPTSIZ0), and status-interrupt (DIEPINTx/)DOEPINT0) registers.
The available set of bits inside the control and transfer size registers slightly differs
from that of other endpoints
● 3 IN endpoints
– each of them can be configured to support the isochronous, bulk or interrupt
transfer type
– each of them has proper control (DIEPCTLx), transfer configuration (DIEPTSIZx),
and status-interrupt (DIEPINTx) registers
– the Device IN endpoints common interrupt mask register (DIEPMSK) is available
to enable/disable a single kind of endpoint interrupt source on all of the IN
endpoints (EP0 included)
– support incomplete isochronous IN transfer interrupt (IISOIXFR bit in
OTG_FS_GINTSTS), asserted when there is at least one isochronous IN endpoint
Doc ID 13902 Rev 9 701/995