STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Ethernet (ETH): media access control (MAC) with DMA controller
RM0008
Bits 8:7 Reserved
Bit 6 WFR: Wakeup frame received
When set, this bit indicates the power management event was generated due to reception of a
wakeup frame. This bit is cleared by a read into this register.
Bit 5 MPR: Magic packet received
When set, this bit indicates the power management event was generated by the reception of a
Magic Packet. This bit is cleared by a read into this register.
Bits 4:3 Reserved
Bit 2 WFE: Wakeup frame enable
When set, this bit enables the generation of a power management event due to wakeup frame
reception.
Bit 1 MPE: Magic Packet enable
When set, this bit enables the generation of a power management event due to Magic Packet
reception.
Bit 0 PD: Power down
When this bit is set, all received frames will be dropped. This bit is cleared automatically when
a magic packet or wakeup frame is received, and Power-down mode is disabled. Frames
received after this bit is cleared are forwarded to the application. This bit must only be set
when either the Magic Packet Enable or Wakeup Frame Enable bit is set high.
Ethernet MAC interrupt status register (ETH_MACSR)
Address offset: 0x0038
Reset value: 0x0000 0000
The ETH_MACSR register contents identify the events in the MAC that can generate an
interrupt.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSTS
MMCTS MMCRS MMCS PMTS
Reserved
Reserved
Reserved
rc_r r r r r
Bits 15:10 Reserved
Bit 9 TSTS: Time stamp trigger status
This bit is set high when the system time value equals or exceeds the value specified in the
Target time high and low registers. This bit is cleared when this register is read.
Bits 8:7 Reserved
Bit 6 MMCTS: MMC transmit status
This bit is set high whenever an interrupt is generated in the ETH_MMCTIR Register. This bit is
cleared when all the bits in this interrupt register (ETH_MMCTIR) are cleared.
Bit 5 MMCRS: MMC receive status
This bit is set high whenever an interrupt is generated in the ETH_MMCRIR register. This bit is
cleared when all the bits in this interrupt register (ETH_MMCRIR) are cleared.
916/995 Doc ID 13902 Rev 9