STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Inter-integrated circuit (I 2 C) interface RM0008 Table 171. I 2 C Interrupt requests (continued) Interrupt event Event flag Enable Control bit Bus error Arbitration loss (Master) Acknowledge failure Overrun/Underrun PEC error Timeout/Tlow error SMBus Alert BERR ARLO AF OVR PECERR TIMEOUT SMBALERT ITERREN Note: 1 SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically ORed on the same interrupt channel. 2 BERR, ARLO, AF, OVR, PECERR, TIMEOUT and SMBALERT are logically ORed on the same interrupt channel. Figure 237. I 2 C interrupt mapping diagram SB ADDR ADD10 ITEVFEN STOPF BTF it_event TxE ITBUFEN RxNE ITERREN BERR ARLO AF OVR PECERR TIMEOUT SMBAlert it_error 24.5 I 2 C debug mode When the microcontroller enters the debug mode (Cortex-M3 core halted), the SMBUS timeout either continues to work normally or stops, depending on the 640/995 Doc ID 13902 Rev 9
RM0008 Inter-integrated circuit (I 2 C) interface DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, refer to Section 29.16.2: Debug support for timers, watchdog, bxCAN and I 2 C on page 972. 24.6 I 2 C registers Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions. 24.6.1 Control register 1 (I2C_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SW NO ALERT PEC POS ACK STOP START RST Res. STRETCH ENGC EN EN SMB SM PE PEC ARP TYPE Res. BUS rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 SWRST: Software reset When set, the I2C is under reset state. Before resetting this bit, make sure the I2C lines are released and the bus is free. 0: I 2 C Peripheral not under reset 1: I 2 C Peripheral under reset state Note: This bit can be used in case the BUSY bit is set to ‘1’ when no stop condition has been detected on the bus. Bit 14 Reserved, forced by hardware to 0. Bit 13 ALERT: SMBus alert This bit is set and cleared by software, and cleared by hardware when PE=0. 0: Releases SMBAlert pin high. Alert Response Address Header followed by NACK. 1: Drives SMBAlert pin low. Alert Response Address Header followed by ACK. Bit 12 PEC: Packet error checking This bit is set and cleared by software, and cleared by hardware when PEC is transferred or by a START or Stop condition or when PE=0. 0: No PEC transfer 1: PEC transfer (in Tx or Rx mode) Note: PEC calculation is corrupted by an arbitration loss. Bit 11 POS: Acknowledge/PEC Position (for data reception) This bit is set and cleared by software and cleared by hardware when PE=0. 0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The PEC bit indicates that current byte in shift register is a PEC. 1: ACK bit controls the (N)ACK of the next byte which will be received in the shift register. The PEC bit indicates that the next byte in the shift register is a PEC Note: The POS bit must be used only in 2-byte reception configuration and must be configured before data reception starts. To NACK the 2nd byte, the ACK bit must be cleared after ADDR is cleared. To check the 2nd byte as PEC, the PEC bit must be set during the ADDR stretch event after configuring the POS bit. Doc ID 13902 Rev 9 641/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Debug support (DBG) DBGMCU_I
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RM0008 Debug support (DBG) Table 20
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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