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Connectivity line devices: reset and clock control (RCC) RM0008 Bits 3:0 PREDIV1[3:0]: PREDIV1 division factor Set and cleared by software to select PREDIV1 division factor. These bits can be written only when PLL is disabled. Note: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the RCC_CFGR register changes Bit(0) accordingly. 0000: PREDIV1 input clock not divided 0001: PREDIV1 input clock divided by 2 0010: PREDIV1 input clock divided by 3 0011: PREDIV1 input clock divided by 4 0100: PREDIV1 input clock divided by 5 0101: PREDIV1 input clock divided by 6 0110: PREDIV1 input clock divided by 7 0111: PREDIV1 input clock divided by 8 1000: PREDIV1 input clock divided by 9 1001: PREDIV1 input clock divided by 10 1010: PREDIV1 input clock divided by 11 1011: PREDIV1 input clock divided by 12 1100: PREDIV1 input clock divided by 13 1101: PREDIV1 input clock divided by 14 1110: PREDIV1 input clock divided by 15 1111: PREDIV1 input clock divided by 16 7.3.13 RCC register map The following table gives the RCC register map and the reset values. Table 16. RCC register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 0x004 0x008 PLL3 RDY PLL3 ON PLL2 RDY PLL2 ON PLL RDY PLLON CSSON HSEBYP HSERDY HSEON Reserved HSIRDY HSION RCC_CR Reser HSICAL[7:0] HSITRIM[4:0] Reserved ved Reset value 0 0 0 0 0 0 0 0 0 0 x x x x x x x x 1 0 0 0 0 1 1 RCC_CFGR Reserved MCO [3:0] Reserved OTGFSPRE PLLMUL [3:0] PLLXTPRE PLLSRC ADC PRE [1:0] PPRE2 [2:0] PPRE1 [2:0] HPRE[3:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCC_CIR Reserved SWS [1:0] SW [1:0] CSSC PLL3RDYC PLL2RDYC PLLRDYC HSERDYC HSIRDYC LSERDYC LSIRDYC Reserved PLL3RDYIE PLL2RDYIE PLLRDYIE HSERDYIE HSIRDYIE LSERDYIE LSIRDYIE CSSF PLL3RDYF PLL2RDYF PLLRDYF HSERDYF HSIRDYF LSERDYF LSIRDYF Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00C RCC_APB2RSTR Reserved Reserved USART1RST Reserved SPI1RST TIM1RST ADC2RST ADC1RST Reserved IOPERST IOPDRST IOPCRST IOPBRST IOPARST Reserved AFIORST Reset value 0 0 0 0 0 0 0 0 0 0 0 0x010 RCC_APB1RSTR Reser ved DACRST PWRRST BKPRST CAN2RST CAN1RST Reserved I2C2RST I2C1RST UART5RST UART4RST USART3RST USART2RST Reserved SPI3RST SPI2RST Reserved WWDGRST Reserved TM7RST TM6RST TM5RST TIM4RST TIM3RST TIM2RST Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 136/995 Doc ID 13902 Rev 9
RM0008 Connectivity line devices: reset and clock control (RCC) Table 16. Offset RCC register map and reset values (continued) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x014 0x018 0x01C 0x020 0x024 RCC_AHBENR Reserved ETHMACRXEN ETHMACTXEN ETHMACEN Reserved OTGFSEN Reserved CRCEN Reserved FLITFEN Reserved SRAMEN DM2AEN DM1AEN Reset value 0 0 0 0 0 1 1 0 0 RCC_APB2ENR Reserved Reserved USART1EN Reserved SPI1EN TIM1EN ADC2EN ADC1EN Reserved IOPEEN IOPDEN IOPCEN IOPBEN IOPAEN Reserved AFIOEN Reset value 0 0 0 0 0 0 0 0 0 0 0 RCC_APB1ENR Reser ved DACEN PWREN BKPEN CAN2EN CAN1EN Reserved I2C2EN I2C1EN UART5EN UART4EN USART3EN USART2EN Reserved SPI3EN SPI2EN Reserved WWDGEN Reserved TIM7EN TIM6EN TIM5EN TIM4EN TIM3EN TIM2EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCC_BDCR Reserved BDRST RTCEN Reserved RTC SEL [1:0] Reserved LSEBYP LSERDY LSEON Reset value 0 0 0 0 0 0 0 RCC_CSR LPWRSTF WWDGRSTF IWDGRSTF SFTRSTF PORRSTF PINRSTF Reserved RMVF Reserved Reset value 0 0 0 0 1 1 0 0 0 LSIRDY LSION 0x028 RCC_AHBSTR Reserved ETHMACRST Reserved OTGFSRST Reset value 0 0 Reserved 0x02C RCC_CFGR2 Reserved I2S3SRC I2S2SRC PREDIV1SRC PLL3MUL [3:0] PLL2MUL [3:0] PREDIV2[3:0] PREDIV1[3:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Table 1 on page 41 for the register boundary addresses. Doc ID 13902 Rev 9 137/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 DMA controller (DMA) not sup
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Pre
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Real-time clock (RTC) RTC pr
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Serial peripheral interface
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RM0008 Universal synchronous asynch
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RM0008 Ethernet (ETH): media access
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RM0008 Device electronic signature
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Debug support (DBG) Note: On
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RM0008 Debug support (DBG) DBGMCU_I
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RM0008 Debug support (DBG) Bits 31:
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) 29.17.9
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RM0008 Revision history 30 Revision
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RM0008 Revision history Table 215.
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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