STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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USB on-the-go full-speed (OTG_FS) RM0008 STUPCNT: SETUP packet count Applies to control OUT Endpoints only. This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 01: 1 packet 10: 2 packets 11: 3 packets Bit 28:19 PKTCNT: Packet count Indicates the total number of USB packets that constitute the Transfer Size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is written to the RxFIFO. Bits 18:0 XFRSIZ: Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the RxFIFO and written to the external memory. 26.14.5 OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) Address offset: 0xE00 Reset value: 0x0000 0000 This register is available in Host and Device modes. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PHYSUSP Reserved GATEHCLK STPPCLK rw rw rw Bit 31:5 Reserved Bit 4 PHYSUSP: PHY Suspended Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended after the application has set the STPPCLK bit (bit 0). Bits 3:2 Reserved Bit 1 GATEHCLK: Gate HCLK The application sets this bit to gate HCLK to modules other than the AHB Slave and Master and wakeup logic when the USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new session starts. Bit 0 STPPCLK: Stop PHY clock The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts. 26.14.6 OTG_FS register map 776/995 Doc ID 13902 Rev 9
RM0008 USB on-the-go full-speed (OTG_FS) Table 187. Offset The table below gives the USB OTG register map and reset values. OTG_FS register map and reset values Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 OTG_FS_GOT GCTL Reserved BSVLD ASVLD DBCT CIDSTS Reserved DHNPEN HSHNPEN HNPRQ HNGSCS Reserved Reset value 0 0 0 1 0 0 0 0 0 0 SRQ SRQSCS 0x004 OTG_FS_GOT GINT Reserved DBCDNE ADTOCHG HNGDET Reserved HNSSCHG SRSSCHG Reserved Reset value 0 0 0 0 0 0 SEDET Res. 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 OTG_FS_GAH BCFG Reserved PTXFELVL TXFELVL Reserved Reset value 0 0 0 OTG_FS_GUS BCFG CTXPKT FDMOD FHMOD Reserved NPTXRWEN TRDT HNPCAP SRPCAP Reserved GINT TOCAL Reset value 0 0 1 0 1 0 0 0 0 0 OTG_FS_GRST CTL AHBIDL Reserved TXFNUM TXFFLSH RXFFLSH Reserved FCRST HSRST CSRST Reset value 1 0 0 0 0 0 0 0 0 0 0 OTG_FS_GINT STS WKUINT SRQINT DISCINT CIDSCHG Reserved PTXFE HCINT HPRTINT Reserved IPXFR/INCOMPISOOUT IISOIXFR OEPINT IEPINT Reserved EOPF ISOODRP ENUMDNE USBRST USBSUSP ESUSP Reserved BOUTNAKEFF GINAKEFF NPTXFE RXFLVL SOF OTGINT MMIS CMOD Reset value 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 OTG_FS_GINT MSK WUIM SRQIM DISCINT CIDSCHGM Reserved PTXFEM HCIM PRTIM Reserved FSUSPM IPXFRM/IISOOXFRM IISOIXFRM OEPINT IEPINT EPMISM Reserved EOPFM ISOODRPM ENUMDNEM USBRST USBSUSPM ESUSPM Reserved GONAKEFFM GINAKEFFM NPTXFEM RXFLVLM SOFM OTGINT MMISM Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_GRXS TSR (Host PKTSTS DPID BCNT CHNUM Reserved mode) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_GRXS TSR (Device FRMNUM PKTSTS DPID BCNT EPNUM Reserved mode) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_GRXS TSR (Host PKTSTS DPID BCNT CHNUM Reserved mode) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_GRXS TSPR (Device FRMNUM PKTSTS DPID BCNT EPNUM Reserved mode) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_GRXF SIZ Reserved RXFD Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Doc ID 13902 Rev 9 777/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Pre
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Ethernet (ETH): media access
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RM0008 Device electronic signature
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Debug support (DBG) DBGMCU_I
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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