STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Debug support (DBG)
Figure 320. Block diagram of STM32F10xxx-level and Cortex-M3-level debug support
STM32F10xxx debug support
Cortex-M3 debug support
Bus matrix
DCode
interface
Cortex-M3
Core
Data
System
interface
JTMS/
SWDIO
JTDI
JTDO/
TRACESWO
NJTRST
JTCK/
SWCLK
SWJ-DP
AHB-AP
Internal private
peripheral bus (PPB)
Bridge
NVIC
DWT
External private
peripheral bus (PPB)
ETM
TPIU
Trace port
TRACESWO
TRACECK
TRACED[3:0]
FPB
ITM
DBGMCU
ai17113
Note:
Note:
The debug features embedded in the Cortex-M3 core are a subset of the ARM CoreSight
Design Kit.
The ARM Cortex-M3 core provides integrated on-chip debug support. It is comprised of:
● SWJ-DP: Serial wire / JTAG debug port
● AHP-AP: AHB access port
● ITM: Instrumentation trace macrocell
● FPB: Flash patch breakpoint
● DWT: Data watchpoint trigger
● TPUI: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
● ETM: Embedded Trace Macrocell (available on larger packages, where the
corresponding pins are mapped)
It also includes debug features dedicated to STM32F10xxx:
● Flexible debug pinout assignment
● MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
For further information on debug functionality supported by the ARM Cortex-M3 core, refer
to the Cortex-M3-r1p1Technical Reference Manual (see Related documents on page 1) and
to the CoreSight Design Kit-r1p0TRM.
Doc ID 13902 Rev 9 953/995