STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

USB on-the-go full-speed (OTG_FS)
RM0008
Figure 269. CSR memory map
0000h
0400h
0800h
0E00h
1000h
2000h
3000h
0F000h
10000h
1 1000h
Core global CSRs (1 Kbyte)
Host mode CSRs (1 Kbyte)
Device mode CSRs (1.5 Kbyte)
Power and clock gating CSRs (0.5 Kbyte)
Device EP 0/Host channel 0 FIFO (4 Kbyte)
Device EP1/Host channel 1 FIFO (4 Kbyte)
Device EP (x – 1) (1) /Host channel (x – 1) (1) FIFO (4 Kbyte)
Device EP x (1) /Host channel x (1) FIFO (4 Kbyte)
DFIFO
push/pop
to this region
Reserved
2 0000h
3 FFFFh
1. x = 3 in Device mode and x = 7 in Host mode.
Direct access to data FIFO RAM
for debugging (128 Kbyte)
DFIFO
debug read/
write to this
region
ai15615
Table 181.
Acronym
Global CSR map
These registers are available in both Host and Device modes.
Core global control and status registers (CSRs)
Address
offset
Register name
OTG_FS_OTGCTL 0x000 OTG_FS control and status register (OTG_FS_GOTGCTL) on page 722
OTG_FS_GOTGINT 0x004 OTG_FS interrupt register (OTG_FS_GOTGINT) on page 725
OTG_FS_GAHBCFG 0x008 OTG_FS AHB configuration register (OTG_FS_GAHBCFG) on page 727
OTG_FS_GUSBCFG 0x00C OTG_FS USB configuration register (OTG_FS_GUSBCFG) on page 728
OTG_FS_GRSTCTL 0x010 OTG_FS reset register (OTG_FS_GRSTCTL) on page 730
OTG_FS_GINTSTS 0x014 OTG_FS core interrupt register (OTG_FS_GINTSTS) on page 732
OTG_FS_GINTMSK 0x018 OTG_FS interrupt mask register (OTG_FS_GINTMSK) on page 736
718/995 Doc ID 13902 Rev 9