STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Ethernet (ETH): media access control (MAC) with DMA controller RM0008 enabled time stamping through CSR, when a valid time stamp value is not available for the frame (for example, because the receive FIFO was full before the time stamp could be written to it), the DMA writes all ones to RDES2 and RDES3. Otherwise (that is, if time stamping is not enabled), RDES2 and RDES3 remain unchanged. Figure 315. Receive DMA operation Start RxDMA Start Stop RxDMA Poll demand/ new frame available (Re-)Fetch next descriptor RxDMA suspended (AHB) error Yes Yes No Frame transfer complete No Own bit set No Yes Yes Flush disabled Frame data available No No Yes Flush the remaining frame Write data to buffer(s) Wait for frame data (AHB) error Yes No Fetch next descriptor (AHB) error Yes No Flush disabled No Own bit set for next desc No Frame transfer complete No Yes Yes Yes Set descriptor error Close RDES0 as intermediate descriptor Time stamp present Yes Write time stamp to RDES2 & RDES3 No Close RDES0 as last descriptor No (AHB) error Yes (AHB) error No Yes ai15643 896/995 Doc ID 13902 Rev 9
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Receive descriptor acquisition The receive engine always attempts to acquire an extra descriptor in anticipation of an incoming frame. Descriptor acquisition is attempted if any of the following conditions is/are satisfied: ● The receive Start/Stop bit (ETH_DMAOMR register[1]) has been set immediately after the DMA has been placed in the Run state. ● The data buffer of the current descriptor is full before the end of the frame currently being transferred ● The controller has completed frame reception, but the current receive descriptor has not yet been closed. ● The receive process has been suspended because of a CPU-owned buffer (RDES0[31] = 0) and a new frame is received. ● A Receive poll demand has been issued. Receive frame processing The MAC transfers the received frames to the STM32F107xx memory only when the frame passes the address filter and the frame size is greater than or equal to the configurable threshold bytes set for the Receive FIFO, or when the complete frame is written to the FIFO in Store-and-forward mode. If the frame fails the address filtering, it is dropped in the MAC block itself (unless Receive All ETH_MACFFR [31] bit is set). Frames that are shorter than 64 bytes, because of collision or premature termination, can be purged from the Receive FIFO. After 64 (configurable threshold) bytes have been received, the DMA block begins transferring the frame data to the receive buffer pointed to by the current descriptor. The DMA sets the first descriptor (RDES0[9]) after the DMA AHB Interface becomes ready to receive a data transfer (if DMA is not fetching transmit data from the memory), to delimit the frame. The descriptors are released when the OWN (RDES0[31]) bit is reset to 0, either as the data buffer fills up or as the last segment of the frame is transferred to the receive buffer. If the frame is contained in a single descriptor, both the last descriptor (RDES0[8]) and first descriptor (RDES0[9]) bits are set. The DMA fetches the next descriptor, sets the last descriptor (RDES0[8]) bit, and releases the RDES0 status bits in the previous frame descriptor. Then the DMA sets the receive interrupt bit (ETH_DMASR register [6]). The same process repeats unless the DMA encounters a descriptor flagged as being owned by the CPU. If this occurs, the receive process sets the receive buffer unavailable bit (ETH_DMASR register[7]) and then enters the Suspend state. The position in the receive list is retained. Receive process suspended If a new receive frame arrives while the receive process is in Suspend state, the DMA refetches the current descriptor in the STM32F107xx memory. If the descriptor is now owned by the DMA, the receive process re-enters the Run state and starts frame reception. If the descriptor is still owned by the host, by default, the DMA discards the current frame at the top of the Rx FIFO and increments the missed frame counter. If more than one frame is stored in the Rx FIFO, the process repeats. The discarding or flushing of the frame at the top of the Rx FIFO can be avoided by setting the DMA Operation mode register bit 24 (DFRF). In such conditions, the receive process sets the receive buffer unavailable status bit and returns to the Suspend state. Doc ID 13902 Rev 9 897/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) transfe
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RM0008 DMA controller (DMA) not sup
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 General-purpose timer (TIMx)
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Pre
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Real-time clock (RTC) RTC pr
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Flexible static memory contr
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RM0008 Controller area network (bxC
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RM0008 Serial peripheral interface
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RM0008 Universal synchronous asynch
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RM0008 Ethernet (ETH): media access
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RM0008 Device electronic signature
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Debug support (DBG) Note: On
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RM0008 Debug support (DBG) DBGMCU_I
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RM0008 Debug support (DBG) Table 20
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RM0008 Debug support (DBG) Bits 31:
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RM0008 Debug support (DBG) Figure 3
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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