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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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USB on-the-go full-speed (OTG_FS)<br />

RM0008<br />

Bit 2 GINSTS: Global IN NAK status<br />

0: A h<strong>and</strong>shake is sent out based on the data availability in the transmit FIFO.<br />

1: A NAK h<strong>and</strong>shake is sent out on all non-periodic IN endpoints, irrespective of the data<br />

availability in the transmit FIFO.<br />

Bit 1 SDIS: Soft disconnect<br />

The application uses this bit to signal the USB OTG core to perform a soft disconnect. As long<br />

as this bit is set, the host does not see that the device is connected, <strong>and</strong> the device does not<br />

receive signals on the USB. The core stays in the disconnected state until the application<br />

clears this bit.<br />

0: Normal operation. When this bit is cleared after a soft disconnect, the core generates a<br />

device connect event to the USB host. When the device is reconnected, the USB host<br />

restarts device enumeration.<br />

1: The core generates a device disconnect event to the USB host.<br />

Bit 0 RWUSIG: Remote wakeup signaling<br />

When the application sets this bit, the core initiates remote signaling to wake up the USB host.<br />

The application must set this bit to instruct the core to exit the Suspend state. As specified in<br />

the USB 2.0 specification, the application must clear this bit 1 ms to 15 ms after setting it.<br />

Table 186 contains the minimum duration (according to device state) for which the Soft<br />

disconnect (SDIS) bit must be set for the USB host to detect a device disconnect. To<br />

accommodate clock jitter, it is recommended that the application add some extra delay to<br />

the specified minimum duration.<br />

Table 186.<br />

Minimum duration for soft disconnect<br />

Operating speed Device state Minimum duration<br />

Full speed Suspended 1 ms + 2.5 µs<br />

Full speed Idle 2.5 µs<br />

Full speed Not Idle or Suspended (Performing transactions) 2.5 µs<br />

OTG_FS device status register (OTG_FS_DSTS)<br />

Address offset: 0x808<br />

Reset value: 0x0000 0010<br />

This register indicates the status of the core with respect to USB-related events. It must be<br />

read on interrupts from the Device all interrupts (OTG_FS_DAINT) register.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Reserved<br />

FNSOF<br />

Reserved<br />

EERR<br />

ENUMSPD<br />

SUSPSTS<br />

r r r r r r r r r r r r r r r r r r<br />

Bits 31:22 Reserved<br />

Bits 21:8 FNSOF: Frame number of the received SOF<br />

Bits 7:4 Reserved<br />

756/995 Doc ID 13902 Rev 9

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