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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Secure digital input/output interface (SDIO)<br />

RM0008<br />

The host can abort reading at any time, within a multiple block operation, regardless of its<br />

type. Transaction abort is done by sending the stop transmission comm<strong>and</strong>.<br />

If the card detects an error (for example, out of range, address misalignment or internal<br />

error) during a multiple block read operation (both types) it stops the data transmission <strong>and</strong><br />

remains in the data state. The host must than abort the operation by sending the stop<br />

transmission comm<strong>and</strong>. The read error is reported in the response to the stop transmission<br />

comm<strong>and</strong>.<br />

If the host sends a stop transmission comm<strong>and</strong> after the card transmits the last block of a<br />

multiple block operation with a predefined number of blocks, it is responded to as an illegal<br />

comm<strong>and</strong>, since the card is no longer in the data state. If the host uses partial blocks whose<br />

accumulated length is not block-aligned <strong>and</strong> block misalignment is not allowed, the card<br />

detects a block misalignment error condition at the beginning of the first misaligned block<br />

(ADDRESS_ERROR error bit is set in the status register).<br />

20.4.7 Stream access, stream write <strong>and</strong> stream read (MultiMediaCard only)<br />

In stream mode, data is transferred in bytes <strong>and</strong> no CRC is appended at the end of each<br />

block.<br />

Stream write (MultiMediaCard only)<br />

WRITE_DAT_UNTIL_STOP (CMD20) starts the data transfer from the SDIO card host to the<br />

card, beginning at the specified address <strong>and</strong> continuing until the SDIO card host issues a<br />

stop comm<strong>and</strong>. When partial blocks are allowed (CSD parameter WRITE_BL_PARTIAL is<br />

set), the data stream can start <strong>and</strong> stop at any address within the card address space,<br />

otherwise it can only start <strong>and</strong> stop at block boundaries. Because the amount of data to be<br />

transferred is not determined in advance, a CRC cannot be used. When the end of the<br />

memory range is reached while sending data <strong>and</strong> no stop comm<strong>and</strong> is sent by the SD card<br />

host, any additional transferred data are discarded.<br />

The maximum clock frequency for a stream write operation is given by the following<br />

equation fields of the card-specific data register:<br />

Maximumspeed=<br />

MIN( TRANSPEED, <br />

------------------------------------------------------------------------<br />

8 2writebllen –<br />

NSAC<br />

)<br />

TAAC R2WFACTOR<br />

● Maximumspeed = maximum write frequency<br />

● TRANSPEED = maximum data transfer rate<br />

● writebllen = maximum write data block length<br />

● NSAC = data read access time 2 in CLK cycles<br />

● TAAC = data read access time 1<br />

● R2WFACTOR = write speed factor<br />

If the host attempts to use a higher frequency, the card may not be able to process the data<br />

<strong>and</strong> stop programming, set the OVERRUN error bit in the status register, <strong>and</strong> while ignoring<br />

all further data transfer, wait (in the receive data state) for a stop comm<strong>and</strong>. The write<br />

operation is also aborted if the host tries to write over a write-protected area. In this case,<br />

however, the card sets the WP_VIOLATION bit.<br />

474/995 Doc ID 13902 Rev 9

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