STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Ethernet (ETH): media access control (MAC) with DMA controller
●
RDES3: Receive descriptor Word3
RDES3 contains the address pointer either to the second data buffer in the descriptor
or to the next descriptor, or it contains time stamp data.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBP2 / RTSH
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 RBAP2 / RTSH: Receive buffer 2 address pointer (next descriptor address) / Receive frame
time stamp high
These bits take on two different functions: the application uses them to indicate to the DMA the
location of where to store the data in memory, and then after transferring all the data the DMA
may use these bits to pass back time stamp data.
RBAP1: When the software makes this descriptor available to the DMA (at the moment that the
OWN bit is set to 1 in RDES0), these bits indicate the physical address of buffer 2 when a
descriptor ring structure is used. If the second address chained (RDES1 [24]) bit is set, this address
contains the pointer to the physical memory where the next descriptor is present. If RDES1 [24] is
set, the buffer (next descriptor) address pointer must be bus width-aligned (RDES3[3, 2, or 1:0]
= 0, corresponding to a bus width of 128, 64 or 32. LSBs are ignored internally.) However, when
RDES1 [24] is reset, there are no limitations on the RDES3 value, except for the following condition:
the DMA uses the configured value for its buffer address generation when the RDES3 value is used to
store the start of frame. The DMA ignores RDES3[3, 2, or 1:0] (corresponding to a bus width of 128,
64 or 32) if the address pointer is to a buffer where the middle or last part of the frame is stored.
RTSH: Before it clears the OWN bt in RDES0, the DMA updates this field with the 32 most
significant bits of the time stamp captured for the corresponding receive frame (overwriting the
value for RBAP2). This field has the time stamp only if time stamping is activated and if the Last
segment control bit (LS) in the descriptor is set.
Rx DMA descriptors format with IEEE1588 time stamp
Figure 317. Receive descriptor fields format with IEEE1588 time stamp enabled
31 0
RDES 0
O
W
N
Status [30:0]
RDES 1
CT
RL
Reserved
[30:29]
Buffer 2 byte count
[28:16]
CTRL
[15:14]
Res.
Buffer 1 byte count
[12:0]
RDES 2
Buffer 1 address [31:0] / Time stamp low [31:0] (1)
RDES 3
Buffer 2 address [31:0] or Next descriptor address [31:0] / Time stamp high[31:0] (1)
ai15645
1. The DMA updates RDES2 and RDES3 with the time stamp value before clearing the OWN bit in RDES0:
RDES2 is updated with the lower 32 time stamp bits (the sub-second field, called RTSL in the RDES2:
Receive descriptor Word2 section) and RDES3 is updated with the upper 32 time stamp bits (the Seconds
field, called RTSH in the RDES3: Receive descriptor Word3 section).
Doc ID 13902 Rev 9 903/995