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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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USB on-the-go full-speed (OTG_FS)<br />

RM0008<br />

Bit 8 HNGSCS: Host negotiation success<br />

The core sets this bit when host negotiation is successful. The core clears this bit when the<br />

HNP Request (HNPRQ) bit in this register is set.<br />

0: Host negotiation failure<br />

1: Host negotiation success<br />

Note: Only accessible in Device mode.<br />

Bits 7:2 Reserved<br />

Bit 1 SRQ: Session request<br />

The application sets this bit to initiate a session request on the USB. The application can clear<br />

this bit by writing a 0 when the host negotiation success status change bit in the OTG Interrupt<br />

register (HNSSCHG bit in OTG_FS_GOTGINT) is set. The core clears this bit when the<br />

HNSSCHG bit is cleared.<br />

If you use the USB 1.1 full-speed serial transceiver interface to initiate the session request, the<br />

application must wait until V BUS discharges to 0.2 V, after the B-Session Valid bit in this register<br />

(BSVLD bit in OTG_FS_GOTGCTL) is cleared. This discharge time varies between different<br />

PHYs <strong>and</strong> can be obtained from the PHY vendor.<br />

0: No session request<br />

1: Session request<br />

Note: Only accessible in Device mode.<br />

Bit 0 SRQSCS: Session request success<br />

The core sets this bit when a session request initiation is successful.<br />

0: Session request failure<br />

1: Session request success<br />

Note: Only accessible in Device mode.<br />

OTG_FS interrupt register (OTG_FS_GOTGINT)<br />

Address offset: 0x04<br />

Reset value: 0x0000 0000<br />

The application reads this register whenever there is an OTG interrupt <strong>and</strong> clears the bits in<br />

this register to clear the OTG interrupt.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Reserved<br />

DBCDNE<br />

ADTOCHG<br />

HNGDET<br />

Reserved<br />

HNSSCHG<br />

SRSSCHG<br />

Reserved<br />

SEDET<br />

Res.<br />

rc_<br />

w1<br />

rc_<br />

w1<br />

rc_<br />

w1<br />

rc_<br />

w1<br />

rc_<br />

w1<br />

rc_<br />

w1<br />

Bits 31:20 Reserved.<br />

Bit 19 DBCDNE: Debounce done<br />

The core sets this bit when the debounce is completed after the device connect. The<br />

application can start driving USB reset after seeing this interrupt. This bit is only valid when the<br />

HNP Capable or SRP Capable bit is set in the Core USB Configuration register (HNPCAP bit or<br />

SRPCAP bit in OTG_FS_GUSBCFG, respectively).<br />

Note: Only accessible in Host mode.<br />

724/995 Doc ID 13902 Rev 9

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