STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Serial peripheral interface (SPI)
RM0008
Note:
When the master clock is generated (MCKOE in the SPI_I2SPR register is set):
F S = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
F S = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
When the master clock is disabled (MCKOE bit cleared):
F S = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
F S = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
Table 166 and Table 167 provide example precision values for different clock configurations.
Other configurations are possible that allow optimum clock precision.
Table 166.
Audio-frequency precision using standard 25 MHz and PLL3 (connectivity line
devices only)
PREDIV2 PLL3 I2SDIV I2SODD
MCLK
Target Real F S (kHz) Error
F S (Hz)
16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit
6 6 14 14 19 9 0 1 No 96000 95942.98 95942.98 0.0594% 0.0594%
7 12 20 14 46 9 1 1 No 48000 48003.07 47971.49 0.0064% 0.0594%
8 8 14 14 31 15 0 1 No 44100 44102.82 44102.82 0.0064% 0.0064%
11 4 16 10 35 30 1 1 No 32000 32010.24 32018.44 0.0320% 0.0576%
8 8 14 14 62 31 0 0 No 22050 22051.41 22051.41 0.0064% 0.0064%
7 11 20 16 139 35 1 1 No 16000 16001.02 16005.12 0.0064% 0.0320%
8 8 14 14 124 62 0 0 No 11025 11025.71 11025.71 0.0064% 0.0064%
9 9 20 20 217 108 0 1 No 8000 8000.512 8000.512 0.0064% 0.0064%
4 4 8 8 2 2 0 0 Yes 96000 97656.25 97656.25 1.7253% 1.7253%
13 13 16 16 2 2 1 1 Yes 48000 48076.92 48076.92 0.1603% 0.1603%
5 5 9 9 4 4 0 0 Yes 44100 43945.31 43945.31 0.3508% 0.3508%
5 5 9 9 5 5 1 1 Yes 32000 31960.22 31960.22 0.1243% 0.1243%
5 5 13 13 11 11 1 1 Yes 22050 22078.80 22078.80 0.1306% 0.1306%
9 9 14 14 9 9 1 1 Yes 16000 15990.49 15990.49 0.0594% 0.0594%
8 8 14 14 15 15 1 1 Yes 11025 11025.70 11025.70 0.0064% 0.0064%
4 4 10 10 30 30 1 1 Yes 8000 8004.611 8004.611 0.0576% 0.0576%
608/995 Doc ID 13902 Rev 9