STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Bit 0 FCB/BPA: Flow control busy/back pressure activate This bit initiates a Pause Control frame in Full-duplex mode and activates the back pressure function in Half-duplex mode if TFCE bit is set. In Full-duplex mode, this bit should be read as 0 before writing to the Flow control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control frame, this bit continues to be set to signify that a frame transmission is in progress. After completion of the Pause control frame transmission, the MAC resets this bit to 0. The Flow control register should not be written to until this bit is cleared. In Half-duplex mode, when this bit is set (and TFCE is set), back pressure is asserted by the MAC core. During back pressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured to Full-duplex mode, the BPA is automatically disabled. Ethernet MAC VLAN tag register (ETH_MACVLANTR) Address offset: 0x001C Reset value: 0x0000 0000 The VLAN tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames. The MAC compares the 13 th and 14 th bytes of the receiving frame (Length/Type) with 0x8100, and the following 2 bytes are compared with the VLAN tag; if a match occurs, the received VLAN bit in the receive frame status is set. The legal length of the frame is increased from 1518 bytes to 1522 bytes. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VLANTC VLANTI rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:17 Reserved Bit 16 VLANTC: 12-bit VLAN tag comparison When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. When this bit is reset, all 16 bits of the received VLAN frame’s fifteenth and sixteenth bytes are used for comparison. Bits 15:0 VLANTI: VLAN tag identifier (for receive frames) This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the user priority, Bit[12] is the canonical format indicator (CFI) and bits[11:0] are the VLAN tag’s VLAN identifier (VID) field. When the VLANTC bit is set, only the VID (bits[11:0]) is used for comparison. If VLANTI (VLANTI[11:0] if VLANTC is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 as VLAN frames. 914/995 Doc ID 13902 Rev 9
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR) Address offset: 0x0028 Reset value: 0x0000 0000 This is the address through which the remote wakeup frame filter registers are written/read by the application. The Wakeup frame filter register is actually a pointer to eight (not transparent) such wakeup frame filter registers. Eight sequential write operations to this address with the offset (0x0028) will write all wakeup frame filter registers. Eight sequential read operations from this address with the offset (0x0028) will read all wakeup frame filter registers. This register contains the higher 16 bits of the 7 th MAC address. Refer to Remote wakeup frame filter register section for additional information. Figure 319. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR) Wakeup frame filter reg0 Wakeup frame filter reg1 Wakeup frame filter reg2 Wakeup frame filter reg3 Filter 0 Byte Mask Filter 1 Byte Mask Filter 2 Byte Mask Filter 3 Byte Mask Wakeup frame filter reg4 RSVD Filter 3 Command RSVD Filter 2 Command RSVD Filter 1 Command RSVD Filter 0 Command Wakeup frame filter reg5 Wakeup frame filter reg6 Wakeup frame filter reg7 Filter 3 Offset Filter 2 Offset Filter 1 Offset Filter 0 Offset Filter 1 CRC - 16 Filter 0 CRC - 16 Filter 3 CRC - 16 Filter 2 CRC - 16 ai15648 Ethernet MAC PMT control and status register (ETH_MACPMTCSR) Address offset: 0x002C Reset value: 0x0000 0000 The ETH_MACPMTCSR programs the request wakeup events and monitors the wakeup events. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WFFRPR Reserved rs Res. rw GU Reserved WFR MPR rc_ r rc_ r Reserved WFE MPE PD rw rw rs Bit 31 WFFRPR: Wakeup frame filter register pointer reset When set, it resets the Remote wakeup frame filter register pointer to 0b000. It is automatically cleared after 1 clock cycle. Bits 30:10 Reserved Bit 9 GU: Global unicast When set, it enables any unicast packet filtered by the MAC (DAF) address recognition to be a wakeup frame. Doc ID 13902 Rev 9 915/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) transfe
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Pre
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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