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Interrupts and events RM0008 In connectivity line devices, Ethernet wakeup events also have the WFE wakeup capability. To use an external line as a wakeup event, refer to Section 9.2.4: Functional description. 9.2.4 Functional description To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register. To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set An interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register. Hardware interrupt selection To configure the 20 lines as interrupt sources, use the following procedure: ● Configure the mask bits of the 20 Interrupt lines (EXTI_IMR) ● Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and EXTI_FTSR) ● Configure the enable and mask bits that control the NVIC IRQ channel mapped to the External Interrupt Controller (EXTI) so that an interrupt coming from one of the 20 lines can be correctly acknowledged. Hardware event selection To configure the 20 lines as event sources, use the following procedure: ● ● Configure the mask bits of the 20 Event lines (EXTI_EMR) Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR) Software interrupt/event selection The 20 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt. ● Configure the mask bits of the 20 Interrupt/Event lines (EXTI_IMR, EXTI_EMR) ● Set the required bit of the software interrupt register (EXTI_SWIER) 9.2.5 External interrupt/event line mapping The 112 GPIOs are connected to the 16 external interrupt/event lines in the following manner: 176/995 Doc ID 13902 Rev 9
RM0008 Interrupts and events Figure 21. External interrupt/event GPIO mapping EXTI0[3:0] bits in AFIO_EXTICR1 register PA0 PB0 PC0 PD0 PE0 PF0 PG0 EXTI0 EXTI1[3:0] bits in AFIO_EXTICR1 register PA1 PB1 PC1 PD1 PE1 PF1 PG1 EXTI1 EXTI15[3:0] bits in AFIO_EXTICR4 register PA15 PB15 PC15 PD15 PE15 PF15 PG15 EXTI15 1. To configure the AFIO_EXTICRx for the mapping of external interrupt/event lines onto GPIOs, the AFIO clock should first be enabled. Refer to Section 6.3.7: APB2 peripheral clock enable register (RCC_APB2ENR) for low-, medium- and high-density devices and, to Section 7.3.7: APB2 peripheral clock enable register (RCC_APB2ENR) for connectivity line devices. The four other EXTI lines are connected as follows: ● ● ● ● EXTI line 16 is connected to the PVD output EXTI line 17 is connected to the RTC Alarm event EXTI line 18 is connected to the USB Wakeup event EXTI line 19 is connected to the Ethernet Wakeup event (available only in connectivity line devices) Doc ID 13902 Rev 9 177/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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