STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Flexible static memory controller (FSMC)
Mode muxed - asynchronous access muxed NOR Flash
Figure 171. Muxed read accesses
Memory transaction
A[25:16]
NADV
NEx
NOE
NWE
High
AD[15:0]
Lower address
1HCLK cycle
data driven
by memory
(ADDSET +1) (DATAST + 1)
2 HCLK
(BUSTURN + 1) (1)
HCLK cycles HCLK cycles cycles HCLK cycles
(ADDHLD + 1)
HCLK cycles
Data sampled Data strobe
ai14728c
1. The bus turnaround delay (BUSTURN + 1) and the delay between side-by-side transactions overlap, so
BUSTURN 5 has not impact.
Figure 172. Muxed write accesses
Memory transaction
A[25:16]
NADV
NEx
NOE
NWE
1HCLK
AD[15:0]
Lower address
data driven by FSMC
(ADDSET +1) ADDHLD (DATAST + 2)
HCLK cycles HCLK cycles HCLK cycles
ai14729c
The difference with mode D is the drive of the lower address byte(s) on the databus.
Doc ID 13902 Rev 9 429/995