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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Universal serial bus full-speed device interface (USB)<br />

RM0008<br />

21 Universal serial bus full-speed device interface (USB)<br />

Low-density devices are <strong>STM32F101xx</strong>, <strong>STM32F102xx</strong> <strong>and</strong> <strong>STM32F103xx</strong><br />

microcontrollers where the Flash memory density ranges between 16 <strong>and</strong> 32 Kbytes.<br />

Medium-density devices are <strong>STM32F101xx</strong>, <strong>STM32F102xx</strong> <strong>and</strong> <strong>STM32F103xx</strong><br />

microcontrollers where the Flash memory density ranges between 64 <strong>and</strong> 128 Kbytes.<br />

High-density devices are <strong>STM32F101xx</strong> <strong>and</strong> <strong>STM32F103xx</strong> microcontrollers where the<br />

Flash memory density ranges between 256 <strong>and</strong> 512 Kbytes.<br />

Connectivity line devices are <strong>STM32F105xx</strong> <strong>and</strong> STM32F107xx microcontrollers.<br />

This section applies to the <strong>STM32F103xx</strong> performance line <strong>and</strong> <strong>STM32F102xx</strong> USB access<br />

line families only.<br />

21.1 USB introduction<br />

The USB peripheral implements an interface between a full-speed USB 2.0 bus <strong>and</strong> the<br />

APB1 bus.<br />

USB suspend/resume are supported which allows to stop the device clocks for low-power<br />

consumption.<br />

21.2 USB main features<br />

Note:<br />

● USB specification version 2.0 full-speed compliant<br />

● Configurable number of endpoints from 1 to 8<br />

● Cyclic redundancy check (CRC) generation/checking, Non-return-to-zero Inverted<br />

(NRZI) encoding/decoding <strong>and</strong> bit-stuffing<br />

● Isochronous transfers support<br />

● Double-buffered bulk/isochronous endpoint support<br />

● USB Suspend/Resume operations<br />

● Frame locked clock pulse generation<br />

The USB <strong>and</strong> CAN share a dedicated 512-byte SRAM memory for data transmission <strong>and</strong><br />

reception, <strong>and</strong> so they cannot be used concurrently (the shared SRAM is accessed through<br />

CAN <strong>and</strong> USB exclusively). The USB <strong>and</strong> CAN can be used in the same application but not<br />

at the same time.<br />

21.3 USB functional description<br />

Figure 190 shows the block diagram of the USB peripheral.<br />

512/995 Doc ID 13902 Rev 9

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