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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

USB on-the-go full-speed (OTG_FS)<br />

c) Setup stage done pattern:<br />

PKTSTS = Setup Stage Done, BCNT = 0x0, EPNUM = Control EP Num,<br />

DPID = Don’t Care (0b00).<br />

These data indicate that the Setup stage for the specified endpoint has completed<br />

<strong>and</strong> the Data stage has started. After this entry is popped from the receive FIFO,<br />

the core asserts a Setup interrupt on the specified control OUT endpoint.<br />

d) Data OUT packet pattern:<br />

PKTSTS = DataOUT, BCNT = size of the received data OUT packet (0 BCNT<br />

1 024), EPNUM = EPNUM on which the packet was received, DPID = Actual<br />

Data PID.<br />

e) Data transfer completed pattern:<br />

PKTSTS = Data OUT Transfer Done, BCNT = 0x0, EPNUM = OUT EP Num<br />

on which the data transfer is complete, DPID = Don’t Care (0b00).<br />

These data indicate that an OUT data transfer for the specified OUT endpoint has<br />

completed. After this entry is popped from the receive FIFO, the core asserts a<br />

Transfer Completed interrupt on the specified OUT endpoint.<br />

5. After the data payload is popped from the receive FIFO, the RXFLVL interrupt<br />

(OTG_FS_GINTSTS) must be unmasked.<br />

6. Steps 1–5 are repeated every time the application detects assertion of the interrupt line<br />

due to RXFLVL in OTG_FS_GINTSTS. Reading an empty receive FIFO can result in<br />

undefined core behavior.<br />

Figure 276 provides a flowchart of the above procedure.<br />

Figure 276. Receive FIFO packet read in slave mode<br />

wait until RXFLVL in OTG_FS_GINTSTSG<br />

rd_data = rd_reg (OTG_FS_GRXSTSP);<br />

Y<br />

rd_data.BCNT = 0<br />

rcv_out_pkt()<br />

N<br />

packet<br />

store in<br />

memory<br />

mem[0:dword_cnt-1] =<br />

rd_rxfifo(rd_data.EPNUM,<br />

dword_cnt)<br />

dword_cnt =<br />

BCNT[11:2] +<br />

(BCNT[1] | BCNT[1])<br />

ai15677<br />

● SETUP transactions<br />

This section describes how the core h<strong>and</strong>les SETUP packets <strong>and</strong> the application’s<br />

sequence for h<strong>and</strong>ling SETUP transactions.<br />

Doc ID 13902 Rev 9 813/995

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