STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

USB on-the-go full-speed (OTG_FS)
RM0008
Figure 273. Bulk/control IN transactions
init_reg(ch_2)
set_ch_en
(ch_2)
set_ch_en
(ch_2)
1
1
2
2
5
Application
init_reg(ch_1)
write_tx_fifo
(ch_1)
write_tx_fifo
(ch_1)
AHB
1
MPS
1
MPS
3
Host
4
ch_1
ch_2
ch_1
USB
Non-Periodic Request
Queue
Assume that this queue
can hold 4 entries.
OUT
Device
ch_2
DAT A0
MPS
set_ch_en
(ch_2)
3
ACK
IN
5
RXFLVL interrupt
4
DAT A0
read_rx_sts
read_rx_fifo
1
MPS
ch_1
ch_2
ACK
OUT
set_ch_en
(ch_2)
ch_2
ch_2
DAT A1
MPS
7
De-allocate
(ch_1)
XFRC interrupt
6
ACK
IN
DAT A1
RXFLVL interrupt
read_rx_stsre
ad_rx_fifo
1
MPS
6
ACK
read_rx_sts
Disable
(ch_2)
7
9
RXFLVL interrupt
XFRC interrupt
RXFLVL interrupt
read_rx_sts
11
10
CHH interrupt r
8
ch_2
De-allocate
(ch_2)
13
12
ai15675
The sequence of operations is as follows:
a) Initialize channel 2.
b) Set the CHENA bit in HCCHAR2 to write an IN request to the non-periodic request
queue.
c) The core attempts to send an IN token after completing the current OUT
transaction.
d) The core generates an RXFLVL interrupt as soon as the received packet is written
to the receive FIFO.
e) In response to the RXFLVL interrupt, mask the RXFLVL interrupt and read the
received packet status to determine the number of bytes received, then read the
receive FIFO accordingly. Following this, unmask the RXFLVL interrupt.
800/995 Doc ID 13902 Rev 9