STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Revision history
RM0008
Table 215.
Document revision history (continued)
Date Revision Changes
08-Feb-2008 3
Figure 4: Power supply overview on page 53 modified.
Section 6.1.2: Power reset on page 75 modified.
Section 6.2: Clocks on page 76 modified.
Definition of Bits 26:24 modified in Section 8.4.2: AF remap and debug I/O
configuration register (AFIO_MAPR) on page 159.
AFIO_EVCR bits corrected in Table 51: AFIO register map and reset values on
page 167.
Number of maskable interrupt channels modified in Section 9.1: Nested
vectored interrupt controller (NVIC) on page 169.
Section 10.3.6: Interrupts on page 187 added. Small text changes.
Examples modified in Figure 90: 6-step generation, COM example
(OSSR=1) on page 283.
Table 73: Output control bits for complementary OCx and OCxN channels
with break feature on page 310 modified.
Register names modified in Section 22.9.4: CAN filter registers on
page 579.
Small text change in Section 24.3.3: I2C master mode on page 630.
Bits 5:0 frequency description modified in Section 24.6.2: Control register 2
(I2C_CR2) on page 643.
Section 21.3.1: Description of USB blocks on page 514 modified.
Section 23.3.4: Simplex communication on page 594 modified.
Section 23.3.6: CRC calculation on page 595 modified.
Note added in BUSY flag on page 595.
Section 23.3.9: Disabling the SPI on page 598 added.
Appendix A: Important notes, removed.
22-May-2008
Reference manual updated to apply to devices containing up to 512 Kbytes
of Flash memory (High-density devices). Document restructured. Small text
changes. Definitions of Medium-density and High-density devices added to
all sections.
In Section 2: Memory and bus architecture on page 38:
– Figure 1: System architecture on page 38, Figure 2: Memory map on
page 39, Table 1: Register boundary addresses on page 41 updated
– Note and text added to AHB/APB bridges (APB) on page 40
– SRAM size in Section 2.3.1: Embedded SRAM on page 42
– Section 2.3.3: Embedded Flash memory on page 44 updated (Flash size,
4
page size, number of pages, Reading the Flash memory, Table 4: Flash
continued
module organization (high-density devices) on page 46 added)
on next
page – Prefetch buffer on/off specified in Reading the Flash memory
bit_number definition modified in Section 2.3.2: Bit banding on page 43.
Section 3: CRC calculation unit on page 50 added (Table 1: Register
boundary addresses on page 41 updated, Figure 2: Memory map on
page 39 updated and CRCEN bit added to Section 6.3.6: AHB peripheral
clock enable register (RCC_AHBENR) on page 93).
Entering Stop mode on page 59 specified.
Updated in Section 5: Backup registers (BKP) on page 66: number of
backup registers and available storage size and Section 5.1: BKP
introduction. ASOE definition modified in Section 5.4.2: RTC clock
calibration register (BKP_RTCCR) on page 68.
984/995 Doc ID 13902 Rev 9