STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Ethernet (ETH): media access control (MAC) with DMA controller
3. The master then sends the slave a Follow_up message, which contains the t 1
information for later use.
4. The slave sends the master a Delay_Req message, noting the exact time, t 3 , at which
this frame leaves the MII.
5. The master receives this message and captures the exact time, t 4 , at which it enters its
system.
6. The master sends the t 4 information to the slave in the Delay_Resp message.
7. The slave uses the four values of t 1 , t 2 , t 3 , and t 4 to synchronize its local timing
reference to the master’s timing reference.
Most of the protocol implementation occurs in the software, above the UDP layer. As
described above, however, hardware support is required to capture the exact time when
specific PTP packets enter or leave the Ethernet port at the MII. This timing information has
to be captured and returned to the software for a proper, high-accuracy implementation of
PTP.
Reference timing source
To get a snapshot of the time, the core requires a reference time in 64-bit format (split into
two 32-bit channels, with the upper 32 bits providing time in seconds, and the lower 32 bits
indicating time in nanoseconds) as defined in the IEEE 1588 specification.
The PTP reference clock input is used to internally generate the reference time (also called
the System Time) and to capture time stamps. The frequency of this reference clock must
be greater than or equal to the resolution of time stamp counter. The synchronization
accuracy target between the master node and the slaves is around 100 ns.
The generation, update and modification of the System Time are described in the Section :
System Time correction methods.
The accuracy depends on the PTP reference clock input period, the characteristics of the
oscillator (drift) and the frequency of the synchronization procedure.
Due to the synchronization from the Tx and Rx clock input domain to the PTP reference
clock domain, the uncertainty on the time stamp latched value is 1 reference clock period. If
we add the uncertainty due to resolution, we will add half the period for time stamping.
Transmission of frames with the PTP feature
When a frame’s SFD is output on the MII, a time stamp is captured. Frames for which time
stamp capture is required are controllable on a per-frame basis. In other words, each
transmitted frame can be marked to indicate whether a time stamp must be captured or not
for that frame. The transmitted frames are not processed to identify PTP frames. Frame
control is exercised through the control bits in the transmit descriptor (as described in
Figure 314: Transmit descriptor field format with IEEE1588 time stamp enabled on
page 891). Captured time stamps are returned to the application in the same way as the
status is provided for frames. The time stamp is sent back along with the Transmit status of
the frame, inside the corresponding transmit descriptor, thus connecting the time stamp
automatically to the specific PTP frame. The 64-bit time stamp information is written back to
the TDES2 and TDES3 fields, with TDES2 holding the time stamp’s 32 least significant bits
as described in Tx DMA descriptor format with IEEE1588 time stamp on page 891.
Doc ID 13902 Rev 9 873/995