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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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USB on-the-go full-speed (OTG_FS)<br />

RM0008<br />

26.10 Peripheral FIFO architecture<br />

Figure 266. Device-mode FIFO address mapping <strong>and</strong> AHB FIFO access mapping<br />

Single data<br />

FIFO<br />

IN endpoint Tx FIFO #n<br />

DFIFO push access<br />

from AHB<br />

IN endpoint Tx FIFO #1<br />

DFIFO push access<br />

from AHB<br />

MAC pop<br />

MAC pop<br />

Dedicated Tx<br />

FIFO #n control<br />

(optional)<br />

.<br />

Dedicated Tx<br />

FIFO #1 control<br />

(optional)<br />

Tx FIFO #n<br />

packet<br />

.<br />

Tx FIFO #1 packet<br />

DIEPTXF2[31:16]<br />

DIEPTXFx[15:0]<br />

.<br />

DIEPTXF2[15:0]<br />

DIEPTXF1[31:16]<br />

DIEPTXF1[15:0]<br />

IN endpoint Tx FIFO #0 Dedicated Tx<br />

DFIFO push access FIFO #0 control<br />

from AHB (optional)<br />

MAC pop<br />

Tx FIFO #0 packet<br />

GNPTXFSIZ[31:16]<br />

GNPTXFSIZ[15:0]<br />

Any OUT endpoint DFIFO pop<br />

access from AHB<br />

Rx FIFO control<br />

Rx packets<br />

GRXFSIZ[31:16]<br />

MAC push<br />

A1 = 0<br />

(Rx start<br />

address<br />

fixed to 0)<br />

ai15611<br />

26.10.1 Peripheral Rx FIFO<br />

The OTG peripheral uses a single receive FIFO that receives the data directed to all OUT<br />

endpoints. Received packets are stacked back-to-back until free space is available in the<br />

Rx-FIFO. The status of the received packet (which contains the OUT endpoint destination<br />

number, the byte count, the data PID <strong>and</strong> the validity of the received data) is also stored by<br />

the PFC on top of the data payload . When no more space is available, host transactions are<br />

NACKed <strong>and</strong> an interrupt is received on the addressed endpoint. The size of the receive<br />

FIFO is configured in the receive FIFO Size register (GRXFSIZ).<br />

The single receive FIFO architecture makes it more efficient for the USB peripheral to fill in<br />

the receive RAM buffer<br />

● all OUT endpoints share the same RAM buffer (shared FIFO)<br />

● the OTG FS Core can fill in the receive FIFO up to the limit for any host sequence of<br />

OUT tokens<br />

The application keeps receiving the Rx-FIFO non-empty interrupt (RXFLVL bit in<br />

OTG_FS_GINTSTS) as long as there is at least one packet available for download. It reads<br />

the packet information from the receive status read <strong>and</strong> pop register (GRXSTSP) <strong>and</strong> finally<br />

pops data off the receive FIFO by reading from the endpoint-related pop address.<br />

712/995 Doc ID 13902 Rev 9

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