29.01.2015 Views

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

USB on-the-go full-speed (OTG_FS)<br />

RM0008<br />

STUPCNT: SETUP packet count<br />

Applies to control OUT Endpoints only.<br />

This field specifies the number of back-to-back SETUP data packets the endpoint can receive.<br />

01: 1 packet<br />

10: 2 packets<br />

11: 3 packets<br />

Bit 28:19 PKTCNT: Packet count<br />

Indicates the total number of USB packets that constitute the Transfer Size amount of data for<br />

this endpoint.<br />

This field is decremented every time a packet (maximum size or short packet) is written to the<br />

RxFIFO.<br />

Bits 18:0 XFRSIZ: Transfer size<br />

This field contains the transfer size in bytes for the current endpoint. The core only interrupts<br />

the application after it has exhausted the transfer size amount of data. The transfer size can be<br />

set to the maximum packet size of the endpoint, to be interrupted at the end of each packet.<br />

The core decrements this field every time a packet is read from the RxFIFO <strong>and</strong> written to the<br />

external memory.<br />

26.14.5 OTG_FS power <strong>and</strong> clock gating control register<br />

(OTG_FS_PCGCCTL)<br />

Address offset: 0xE00<br />

Reset value: 0x0000 0000<br />

This register is available in Host <strong>and</strong> Device modes.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Reserved<br />

PHYSUSP<br />

Reserved<br />

GATEHCLK<br />

STPPCLK<br />

rw rw rw<br />

Bit 31:5 Reserved<br />

Bit 4 PHYSUSP: PHY Suspended<br />

Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended<br />

after the application has set the STPPCLK bit (bit 0).<br />

Bits 3:2 Reserved<br />

Bit 1 GATEHCLK: Gate HCLK<br />

The application sets this bit to gate HCLK to modules other than the AHB Slave <strong>and</strong> Master<br />

<strong>and</strong> wakeup logic when the USB is suspended or the session is not valid. The application<br />

clears this bit when the USB is resumed or a new session starts.<br />

Bit 0 STPPCLK: Stop PHY clock<br />

The application sets this bit to stop the PHY clock when the USB is suspended, the session is<br />

not valid, or the device is disconnected. The application clears this bit when the USB is<br />

resumed or a new session starts.<br />

26.14.6 OTG_FS register map<br />

776/995 Doc ID 13902 Rev 9

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!