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Real-time clock (RTC) RM0008 16.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) The RTC core has one 32-bit programmable counter, accessed through two 16-bit registers; the count rate is based on the TR_CLK time reference, generated by the prescaler. RTC_CNT registers keep the counting value of this counter. They are write-protected by bit RTOFF in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. A write operation on the upper (RTC_CNTH) or lower (RTC_CNTL) registers directly loads the corresponding programmable counter and reloads the RTC Prescaler. When reading, the current value in the counter (system date) is returned. RTC counter register high (RTC_CNTH) Address offset: 0x18 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_CNT[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 RTC_CNT[31:16]: RTC counter high Reading the RTC_CNTH register, the current value of the high part of the RTC Counter register is returned. To write to this register it is necessary to enter configuration mode (see Section 16.3.4: Configuring RTC registers on page 390). RTC counter register low (RTC_CNTL) Address offset: 0x1C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 RTC_CNT[15:0]: RTC counter low Reading the RTC_CNTL register, the current value of the lower part of the RTC Counter register is returned. To write to this register it is necessary to enter configuration mode (see Section 16.3.4: Configuring RTC registers on page 390). 396/995 Doc ID 13902 Rev 9
RM0008 Real-time clock (RTC) 16.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) When the programmable counter reaches the 32-bit value stored in the RTC_ALR register, an alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. RTC alarm register high (RTC_ALRH) Address offset: 0x20 Write only (see Section 16.3.4 on page 390) Reset value: 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_ALR[31:16] w w w w w w w w w w w w w w w w Bits 15:0 RTC_ALR[31:16]: RTC alarm high The high part of the alarm time is written by software in this register. To write to this register it is necessary to enter configuration mode (see Section 16.3.4: Configuring RTC registers on page 390). RTC alarm register low (RTC_ALRL) Address offset: 0x24 Write only (see Section 16.3.4 on page 390) Reset value: 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_ALR[15:0] w w w w w w w w w w w w w w w w Bits 15:0 RTC_ALR[15:0]: RTC alarm low The low part of the alarm time is written by software in this register. To write to this register it is necessary to enter configuration mode (see Section 16.3.4: Configuring RTC registers on page 390). Doc ID 13902 Rev 9 397/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Ethernet (ETH): media access
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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