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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

Secure digital input/output interface (SDIO)<br />

Table 128.<br />

Card status (continued)<br />

Bits Identifier Type Value Description<br />

Clear<br />

condition<br />

19 ERROR E X<br />

’0’= no error<br />

’1’= error<br />

(Undefined by the st<strong>and</strong>ard) A generic<br />

card error related to the (<strong>and</strong> detected<br />

during) execution of the last host<br />

comm<strong>and</strong> (e.g. read or write failures).<br />

C<br />

18 Reserved<br />

17 Reserved<br />

16 CID/CSD_OVERWRITE E X<br />

’0’= no error ‘1’=<br />

error<br />

Can be either of the following errors:<br />

– The CID register has already been<br />

written <strong>and</strong> cannot be overwritten<br />

– The read-only section of the CSD does<br />

not match the card contents<br />

– An attempt to reverse the copy (set as<br />

original) or permanent WP<br />

(unprotected) bits was made<br />

C<br />

15 WP_ERASE_SKIP E X<br />

’0’= not protected<br />

’1’= protected<br />

Set when only partial address space<br />

was erased due to existing write<br />

C<br />

14 CARD_ECC_DISABLED S X<br />

’0’= enabled<br />

’1’= disabled<br />

The comm<strong>and</strong> has been executed without<br />

using the internal ECC.<br />

A<br />

13 ERASE_RESET<br />

’0’= cleared<br />

’1’= set<br />

An erase sequence was cleared before<br />

executing because an out of erase<br />

sequence comm<strong>and</strong> was received<br />

(comm<strong>and</strong>s other than CMD35, CMD36,<br />

CMD38 or CMD13)<br />

C<br />

12:9 CURRENT_STATE S R<br />

0 = Idle<br />

1 = Ready<br />

2 = Ident<br />

3 = Stby<br />

4 = Tran<br />

5 = Data<br />

6 = Rcv<br />

7 = Prg<br />

8 = Dis<br />

9 = Btst<br />

10-15 = reserved<br />

The state of the card when receiving the<br />

comm<strong>and</strong>. If the comm<strong>and</strong> execution<br />

causes a state change, it will be visible to<br />

the host in the response on the next<br />

comm<strong>and</strong>. The four bits are interpreted as<br />

a binary number between 0 <strong>and</strong> 15.<br />

B<br />

8 READY_FOR_DATA S R<br />

’0’= not ready ‘1’<br />

= ready<br />

Corresponds to buffer empty signalling on<br />

the bus<br />

7 SWITCH_ERROR E X<br />

’0’= no error<br />

’1’= switch error<br />

If set, the card did not switch to the<br />

expected mode as requested by the<br />

SWITCH comm<strong>and</strong><br />

B<br />

6 Reserved<br />

5 APP_CMD S R<br />

‘0’ = Disabled<br />

‘1’ = Enabled<br />

The card will expect ACMD, or an<br />

indication that the comm<strong>and</strong> has been<br />

interpreted as ACMD<br />

C<br />

4 Reserved for SD I/O Card<br />

Doc ID 13902 Rev 9 481/995

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