STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Ethernet (ETH): media access control (MAC) with DMA controller
RM0008
RMII clock sources
As described in the RMII clock sources section, the STM32F107xx could provide this
50 MHz clock signal on its MCO output pin and you then have to configure this output value
through PLL configuration.
Figure 291. RMII clock sources
STM32
25 MHz
802.3 MAC
External
PHY
PLL
REF_CLK
MCO
50 MHz
For 10/100 Mbit/s
50 MHz
ai15625
27.4.4 MII/RMII selection
The mode, MII or RMII, is selected using the configuration bit 23, MII_RMII_SEL, in the
AFIO_MAPR register. The application has to set the MII/RMII mode while the Ethernet
controller is under reset or before enabling the clocks.
MII/RMII internal clock scheme
The clock scheme required to support both the MII and RMII, as well as 10 and 100 Mbit/s
operations is described in Figure 292.
Figure 292. Clock scheme
MAC
MII_TX_CLK as AF
(25 MHz or 2.5 MHz)
MII_RX_CLK as AF
(25 MHz or 2.5 MHz)
RMII_REF_CK as AF
(50 MHz)
GPIO and AF
controller
GPIO and AF
controller
25 MHz or 2.5 MHz
50 MHz
Sync. divider
/2 for 100 Mb/s
/20 for 10 Mb/s
25 MHz or 2.5 MHz
0 25 MHz
1 or 2.5 MHz
0 MII
1 RMII (1)
0
1
25 MHz
or 2.5 MHz
MACTXCLK
MACRXCLK
TX
RX
RMII
AHB
HCLK
must be greater
than 25 MHz
HCLK
ai15650
1. The MII/RMII selection is controlled through bit 23, MII_RMII_SEL, in the AFIO_MAPR register.
848/995 Doc ID 13902 Rev 9