STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Flexible static memory controller (FSMC)
RM0008
Figure 173. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)
Memory transaction = burst of 4 half words
HCLK
CLK
A[25:16]
addr[25:16]
NEx
NOE
NWE
High
NADV
NWAIT
(WAITCFG = 0)
NWAIT
(WAITCFG = 1)
DATALAT CLK cycles
inserted wait state
A/D[15:0]
Addr[15:0] data data data data
1 clock
cycle
1 clock
cycle
Data strobes
Data strobes
ai14730
1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held
low.
Table 109.
FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-20 0x0000
19 CBURSTRW No effect on synchronous read
18-15 0x0
14 EXTMOD 0x0
13 WAITEN
12 WREN no effect on synchronous read
When high, the first data after latency period is taken as always
valid, regardless of the wait from memory value
432/995 Doc ID 13902 Rev 9