STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

USB on-the-go full-speed (OTG_FS)
RM0008
Table 187. OTG_FS register map and reset values (continued)
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0xCF0
OTG_FS_DOEP
TSIZ15
Reserved
RXDPID/
STUPCNT
PKTCNT
XFRSIZ
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xE00
OTG_FS_PCG
CCTL
Reset value
Reserved
PHYSUSP
Reserved
GATEHCLK
STPPCLK
Refer to Table 1 on page 41 for the register boundary addresses.
26.15 OTG_FS programming model
26.15.1 Core initialization
The application must perform the core initialization sequence. If the cable is connected
during power-up, the current mode of operation bit in the Core interrupt register (CMOD bit
in OTG_FS_GINTSTS) reflects the mode. The OTG_FS controller enters Host mode when
an “A” plug is connected or Device mode when a “B” plug is connected.
This section explains the initialization of the OTG_FS controller after power-on. The
application must follow the initialization sequence irrespective of Host or Device mode
operation. All core global registers are initialized according to the core’s configuration:
1. Program the following fields in the Global AHB configuration (OTG_FS_GAHBCFG)
register:
– Global interrupt mask bit GINT = 1
– RxFIFO non-empty (RXFLVL bit in OTG_FS_GINTSTS)
– Periodic TxFIFO empty level
2. Program the following fields in OTG_FS_GUSBCFG register:
– HNP capable bit
– SRP capable bit
– FS timeout calibration field
– USB turnaround time field
3. The software must unmask the following bits in the GINTMSK register:
OTG interrupt mask
Mode mismatch interrupt mask
4. The software can read the CMOD bit in OTG_FS_GINTSTS to determine whether the
OTG_FS controller is operating in Host or Device mode.
792/995 Doc ID 13902 Rev 9