STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Ethernet (ETH): media access control (MAC) with DMA controller
Ethernet MAC hash table low register (ETH_MACHTLR)
Address offset: 0x000C
Reset value: 0x0000 0000
The Hash table low register contains the lower 32 bits of the multi-cast Hash table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTL
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 HTL: Hash table low
This field contains the lower 32 bits of the Hash table.
Ethernet MAC MII address register (ETH_MACMIIAR)
Address offset: 0x0010
Reset value: 0x0000 0000
The MII address register controls the management cycles to the external PHY through the
management interface.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PA
MR
Reserved
CR MW MB
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rc_
w1
Bits 31:16 Reserved
Bits 15:11 PA: PHY address
This field tells which of the 32 possible PHY devices are being accessed.
Bits 10:6 MR: MII register
These bits select the desired MII register in the selected PHY device.
Bit 5 Reserved
Bits 4:2 CR: Clock range
The CR clock range selection determines the HCLK frequency and is used to decide the
frequency of the MDC clock:
Selection HCLK MDC Clock
000 60-72 MHz HCLK/42
001 Reserved -
010 20-35 MHz HCLK/16
011 35-60 MHz HCLK/26
100, 101, 110, 111 Reserved -
Bit 1 MW: MII write
When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If
this bit is not set, this will be a Read operation, placing the data in the MII Data register.
Doc ID 13902 Rev 9 911/995