STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Serial peripheral interface (SPI)
RM0008
23.5.9 SPI_I 2 S prescaler register (SPI_I2SPR)
Address offset: 20h
Reset value: 0000 0010 (0002h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved MCKOE ODD I2SDIV
Res. rw rw rw
Bits 15:10 Reserved: Forced to 0 by hardware
Bit 9 MCKOE: Master clock output enable
0: Master clock output is disabled
1: Master clock output is enabled
Note: This bit should be configured when the I 2 S is disabled. It is used only when the I 2 S is in master
mode.
Not used in SPI mode.
Bit 8 ODD: Odd factor for the prescaler
0: real divider value is = I2SDIV *2
1: real divider value is = (I2SDIV * 2)+1
Refer to Section 23.4.3 on page 607
Note: This bit should be configured when the I 2 S is disabled. It is used only when the I 2 S is in master
mode.
Not used in SPI mode
Bit 7:0 I2SDIV: I2S Linear prescaler
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
Refer to Section 23.4.3 on page 607
Note: These bits should be configured when the I 2 S is disabled. It is used only when the I 2 S is in
master mode.
Not used in SPI mode.
622/995 Doc ID 13902 Rev 9